tlc5615.tan.rpt

这是一款用VHDL语言编写的对外部DA芯片的控制程序

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K100QC208-3     ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Minimum tpd to report                                 ; 0.0NS              ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; Off                ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                          ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                   ; To                                                                     ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 71.94 MHz ( period = 13.900 ns )                    ; ctrl:HH|cter[7]                                                        ; ctrl:HH|lpm_counter:mem_addr_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk        ; clk      ; None                        ; None                      ; 12.100 ns               ;
; N/A                                     ; 71.94 MHz ( period = 13.900 ns )                    ; ctrl:HH|cter[7]                                                        ; ctrl:HH|lpm_counter:mem_addr_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk        ; clk      ; None                        ; None                      ; 12.100 ns               ;
; N/A                                     ; 71.94 MHz ( period = 13.900 ns )                    ; ctrl:HH|cter[7]                                                        ; ctrl:HH|lpm_counter:mem_addr_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk        ; clk      ; None                        ; None                      ; 12.100 ns               ;
; N/A                                     ; 71.94 MHz ( period = 13.900 ns )                    ; ctrl:HH|cter[7]                                                        ; ctrl:HH|lpm_counter:mem_addr_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; clk        ; clk      ; None                        ; None                      ; 12.100 ns               ;
; N/A                                     ; 71.94 MHz ( period = 13.900 ns )                    ; ctrl:HH|cter[7]                                                        ; ctrl:HH|lpm_counter:mem_addr_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clk        ; clk      ; None                        ; None                      ; 12.100 ns               ;
; N/A                                     ; 71.94 MHz ( period = 13.900 ns )                    ; ctrl:HH|cter[7]                                                        ; ctrl:HH|lpm_counter:mem_addr_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; clk        ; clk      ; None                        ; None                      ; 12.100 ns               ;
; N/A                                     ; 72.99 MHz ( period = 13.700 ns )                    ; ctrl:HH|cter[6]                                                        ; ctrl:HH|lpm_counter:mem_addr_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk        ; clk      ; None                        ; None                      ; 11.900 ns               ;
; N/A                                     ; 72.99 MHz ( period = 13.700 ns )                    ; ctrl:HH|cter[6]                                                        ; ctrl:HH|lpm_counter:mem_addr_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk        ; clk      ; None                        ; None                      ; 11.900 ns               ;