📄 tlc5615.rpt
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- 5 - F 08 OR2 s 0 4 0 4 |sin_rom:HJ|~1194~1
- 4 - F 02 OR2 s ! 0 4 0 2 |sin_rom:HJ|~1194~2
- 7 - F 10 OR2 s 0 4 0 1 |sin_rom:HJ|~1194~3
- 8 - F 04 OR2 s 0 4 0 3 |sin_rom:HJ|~1201~1
- 7 - F 12 OR2 s 0 4 0 2 |sin_rom:HJ|~1201~2
- 4 - F 16 AND2 s 0 4 0 2 |sin_rom:HJ|~1201~3
- 3 - F 12 OR2 s 0 4 0 4 |sin_rom:HJ|~1201~4
- 5 - F 02 OR2 s 0 4 0 3 |sin_rom:HJ|~1201~5
- 8 - F 32 OR2 s 0 4 0 5 |sin_rom:HJ|~1201~6
- 1 - F 15 OR2 s 0 2 0 1 |sin_rom:HJ|~1201~7
- 3 - F 04 OR2 s 0 2 0 2 |sin_rom:HJ|~1201~8
- 4 - F 14 OR2 s 0 3 0 1 |sin_rom:HJ|~1201~9
- 7 - F 16 OR2 s 0 4 0 1 |sin_rom:HJ|~1201~10
- 8 - F 16 OR2 s 0 4 0 1 |sin_rom:HJ|~1201~11
- 8 - F 12 OR2 s 0 4 0 2 |sin_rom:HJ|~1208~1
- 8 - F 08 OR2 s 0 4 0 2 |sin_rom:HJ|~1208~2
- 5 - F 18 OR2 s ! 0 4 0 2 |sin_rom:HJ|~1208~3
- 8 - F 05 AND2 s ! 0 3 0 2 |sin_rom:HJ|~1208~4
- 2 - F 10 OR2 s 0 4 0 3 |sin_rom:HJ|~1208~5
- 4 - F 08 OR2 s 0 4 0 3 |sin_rom:HJ|~1208~6
- 5 - F 05 OR2 s 0 4 0 1 |sin_rom:HJ|~1208~7
- 6 - F 05 OR2 s 0 4 0 1 |sin_rom:HJ|~1208~8
- 7 - F 05 OR2 s 0 4 0 1 |sin_rom:HJ|~1208~9
- 2 - F 18 OR2 s 0 4 0 2 |sin_rom:HJ|~1215~1
- 4 - F 32 OR2 s ! 0 4 0 3 |sin_rom:HJ|~1215~2
- 4 - F 12 OR2 s 0 2 0 2 |sin_rom:HJ|~1215~3
- 5 - F 04 OR2 s 0 4 0 2 |sin_rom:HJ|~1215~4
- 1 - F 13 OR2 s 0 3 0 1 |sin_rom:HJ|~1215~5
- 5 - F 06 OR2 s ! 0 4 0 3 |sin_rom:HJ|~1222~1
- 7 - F 04 OR2 s 0 4 0 3 |sin_rom:HJ|~1222~2
- 7 - F 18 OR2 s ! 0 4 0 1 |sin_rom:HJ|~1222~3
- 8 - F 18 OR2 s 0 4 0 2 |sin_rom:HJ|~1222~4
- 4 - F 10 OR2 s 0 4 0 2 |sin_rom:HJ|~1222~5
- 8 - F 06 OR2 s 0 3 0 2 |sin_rom:HJ|~1222~6
- 8 - F 10 OR2 s 0 4 0 2 |sin_rom:HJ|~1222~7
- 3 - F 11 OR2 s 0 4 0 1 |sin_rom:HJ|~1222~8
- 1 - F 11 OR2 s ! 0 3 0 2 |sin_rom:HJ|~1229~1
- 6 - F 07 OR2 s ! 0 4 0 2 |sin_rom:HJ|~1229~2
- 6 - F 18 OR2 s ! 0 4 0 2 |sin_rom:HJ|~1229~3
- 1 - F 17 OR2 s 0 3 0 1 |sin_rom:HJ|~1229~4
- 3 - F 17 OR2 s 0 4 0 1 |sin_rom:HJ|~1229~5
- 4 - F 17 OR2 s 0 4 0 1 |sin_rom:HJ|~1229~6
- 1 - F 07 OR2 s 0 4 0 2 |sin_rom:HJ|~1229~7
- 4 - F 05 OR2 s 0 3 0 2 |sin_rom:HJ|~1229~8
- 6 - F 08 OR2 s ! 0 4 0 4 |sin_rom:HJ|~1236~1
- 2 - F 04 OR2 s ! 0 4 0 2 |sin_rom:HJ|~1236~2
- 4 - F 04 OR2 s ! 0 4 0 2 |sin_rom:HJ|~1236~3
- 1 - F 18 OR2 s 0 4 0 4 |sin_rom:HJ|~1236~4
- 3 - F 20 OR2 s 0 4 0 1 |sin_rom:HJ|~1236~5
- 4 - F 20 OR2 s 0 3 0 1 |sin_rom:HJ|~1236~6
- 8 - F 20 AND2 s 0 4 0 1 |sin_rom:HJ|~1236~7
- 6 - F 20 OR2 s 0 4 0 1 |sin_rom:HJ|~1236~8
- 2 - F 06 OR2 s 0 4 0 2 |sin_rom:HJ|~1236~9
- 3 - F 16 OR2 s 0 4 0 2 |sin_rom:HJ|~1236~10
- 2 - F 15 AND2 s 0 2 0 1 |sin_rom:HJ|~1243~1
- 3 - F 15 OR2 s 0 4 0 1 |sin_rom:HJ|~1243~2
- 2 - F 07 DFFE + 0 2 0 1 |sin_rom:HJ|:1250
- 2 - F 03 DFFE + 0 3 0 1 |sin_rom:HJ|:1251
- 1 - F 10 DFFE + 0 3 0 1 |sin_rom:HJ|:1252
- 1 - F 16 DFFE + 0 3 0 1 |sin_rom:HJ|:1253
- 2 - F 05 DFFE + 0 3 0 1 |sin_rom:HJ|:1254
- 2 - F 13 DFFE + 0 4 0 2 |sin_rom:HJ|:1255
- 6 - F 10 DFFE + 0 3 0 1 |sin_rom:HJ|:1256
- 5 - F 17 DFFE + 0 3 0 1 |sin_rom:HJ|:1257
- 3 - F 05 DFFE + 0 3 0 1 |sin_rom:HJ|:1258
- 5 - F 15 DFFE + 0 3 0 1 |sin_rom:HJ|:1259
- 1 - A 25 OR2 ! 0 2 0 2 |tlc5615_1:TLC|lpm_add_sub:429|addcore:adder|:75
- 3 - A 25 OR2 ! 0 2 0 2 |tlc5615_1:TLC|lpm_add_sub:429|addcore:adder|:79
- 2 - A 25 OR2 ! 0 2 0 4 |tlc5615_1:TLC|lpm_add_sub:429|addcore:adder|:83
- 4 - B 36 AND2 0 2 0 1 |tlc5615_1:TLC|lpm_add_sub:430|addcore:adder|:55
- 7 - B 29 AND2 0 3 0 1 |tlc5615_1:TLC|lpm_add_sub:430|addcore:adder|:59
- 7 - B 31 DFFE + ! 1 1 0 2 |tlc5615_1:TLC|ncs_d (|tlc5615_1:TLC|:18)
- 2 - B 29 OR2 ! 0 4 0 1 |tlc5615_1:TLC|:25
- 6 - B 31 DFFE + ! 1 3 1 8 |tlc5615_1:TLC|:36
- 1 - A 33 OR2 0 3 0 5 |tlc5615_1:TLC|:48
- 1 - A 26 AND2 s ! 0 4 0 4 |tlc5615_1:TLC|~98~1
- 5 - A 33 AND2 0 3 0 1 |tlc5615_1:TLC|:98
- 2 - A 33 OR2 s 0 4 0 5 |tlc5615_1:TLC|~140~1
- 3 - A 26 DFFE + 1 0 0 1 |tlc5615_1:TLC|cter8 (|tlc5615_1:TLC|:154)
- 2 - A 26 DFFE + 1 0 0 1 |tlc5615_1:TLC|cter7 (|tlc5615_1:TLC|:155)
- 4 - A 26 DFFE + 1 0 0 1 |tlc5615_1:TLC|cter6 (|tlc5615_1:TLC|:156)
- 5 - A 26 DFFE + 1 0 0 1 |tlc5615_1:TLC|cter5 (|tlc5615_1:TLC|:157)
- 4 - A 33 DFFE + 1 3 0 3 |tlc5615_1:TLC|cter4 (|tlc5615_1:TLC|:158)
- 7 - A 25 DFFE + 1 3 0 1 |tlc5615_1:TLC|cter3 (|tlc5615_1:TLC|:159)
- 6 - A 25 DFFE + 1 3 0 1 |tlc5615_1:TLC|cter2 (|tlc5615_1:TLC|:160)
- 4 - A 25 DFFE + 1 3 0 1 |tlc5615_1:TLC|cter1 (|tlc5615_1:TLC|:161)
- 5 - A 25 DFFE + 1 2 0 2 |tlc5615_1:TLC|cter0 (|tlc5615_1:TLC|:162)
- 6 - A 33 DFFE + 1 1 0 2 |tlc5615_1:TLC|clk250 (|tlc5615_1:TLC|:174)
- 7 - A 33 DFFE + 1 1 0 1 |tlc5615_1:TLC|clk250_d (|tlc5615_1:TLC|:176)
- 3 - A 33 DFFE + ! 1 3 1 3 |tlc5615_1:TLC|:197
- 6 - B 36 DFFE + 1 1 0 2 |tlc5615_1:TLC|scl_d (|tlc5615_1:TLC|:199)
- 1 - B 36 OR2 ! 0 2 0 5 |tlc5615_1:TLC|:200
- 5 - B 29 OR2 ! 0 4 0 2 |tlc5615_1:TLC|:208
- 6 - B 29 OR2 0 4 0 1 |tlc5615_1:TLC|:245
- 8 - B 29 DFFE + 1 3 0 3 |tlc5615_1:TLC|scounter3 (|tlc5615_1:TLC|:255)
- 2 - B 36 DFFE + 1 3 0 4 |tlc5615_1:TLC|scounter2 (|tlc5615_1:TLC|:256)
- 3 - B 29 DFFE + 1 2 0 6 |tlc5615_1:TLC|scounter1 (|tlc5615_1:TLC|:257)
- 4 - B 29 DFFE + 1 3 0 5 |tlc5615_1:TLC|scounter0 (|tlc5615_1:TLC|:258)
- 3 - B 31 AND2 0 3 0 10 |tlc5615_1:TLC|:321
- 5 - B 36 AND2 0 3 0 10 |tlc5615_1:TLC|:337
- 7 - F 03 OR2 0 3 0 1 |tlc5615_1:TLC|:359
- 4 - F 03 OR2 0 3 0 1 |tlc5615_1:TLC|:360
- 8 - F 09 OR2 0 3 0 1 |tlc5615_1:TLC|:361
- 5 - F 09 OR2 0 3 0 1 |tlc5615_1:TLC|:362
- 7 - F 13 OR2 0 3 0 1 |tlc5615_1:TLC|:363
- 4 - F 13 OR2 0 3 0 1 |tlc5615_1:TLC|:364
- 3 - F 09 OR2 0 3 0 1 |tlc5615_1:TLC|:365
- 7 - F 17 OR2 0 3 0 1 |tlc5615_1:TLC|:366
- 8 - F 15 OR2 0 3 0 1 |tlc5615_1:TLC|:367
- 1 - F 03 DFFE + 1 3 0 2 |tlc5615_1:TLC|reg_data9 (|tlc5615_1:TLC|:389)
- 5 - F 03 DFFE + 1 3 0 2 |tlc5615_1:TLC|reg_data8 (|tlc5615_1:TLC|:390)
- 2 - F 09 DFFE + 1 3 0 2 |tlc5615_1:TLC|reg_data7 (|tlc5615_1:TLC|:391)
- 6 - F 09 DFFE + 1 3 0 2 |tlc5615_1:TLC|reg_data6 (|tlc5615_1:TLC|:392)
- 8 - F 13 DFFE + 1 3 0 2 |tlc5615_1:TLC|reg_data5 (|tlc5615_1:TLC|:393)
- 5 - F 13 DFFE + 1 3 0 2 |tlc5615_1:TLC|reg_data4 (|tlc5615_1:TLC|:394)
- 1 - F 09 DFFE + 1 3 0 2 |tlc5615_1:TLC|reg_data3 (|tlc5615_1:TLC|:395)
- 8 - F 17 DFFE + 1 3 0 2 |tlc5615_1:TLC|reg_data2 (|tlc5615_1:TLC|:396)
- 4 - F 15 DFFE + 1 3 0 2 |tlc5615_1:TLC|reg_data1 (|tlc5615_1:TLC|:397)
- 7 - F 15 DFFE + 1 3 0 1 |tlc5615_1:TLC|reg_data0 (|tlc5615_1:TLC|:398)
- 1 - B 29 OR2 s ! 0 4 0 1 |tlc5615_1:TLC|~427~1
- 3 - B 36 DFFE + ! 1 3 1 0 |tlc5615_1:TLC|:428
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\work\tlc5615_max\tlc5615.rpt
tlc5615
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/144( 4%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 20/144( 13%) 0/ 72( 0%) 1/ 72( 1%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 85/144( 59%) 11/ 72( 15%) 1/ 72( 1%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
33: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\work\tlc5615_max\tlc5615.rpt
tlc5615
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 66 clk
Device-Specific Information: f:\work\tlc5615_max\tlc5615.rpt
tlc5615
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 56 rst
Device-Specific Information: f:\work\tlc5615_max\tlc5615.rpt
tlc5615
** EQUATIONS **
clk : INPUT;
rst : INPUT;
-- Node name is 'SCL'
-- Equation name is 'SCL', type is output
SCL = _LC3_A33;
-- Node name is 'SIN'
-- Equation name is 'SIN', type is output
SIN = _LC3_B36;
-- Node name is 'SNCS'
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