📄 rom16_8.rpt
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Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch10\rom16_8.rpt
rom16_8
** EQUATIONS **
ADDR0 : INPUT;
ADDR1 : INPUT;
ADDR2 : INPUT;
ADDR3 : INPUT;
CE : INPUT;
-- Node name is 'DATAOUT0'
-- Equation name is 'DATAOUT0', type is output
DATAOUT0 = _LC7_A1;
-- Node name is 'DATAOUT1'
-- Equation name is 'DATAOUT1', type is output
DATAOUT1 = _LC1_A4;
-- Node name is 'DATAOUT2'
-- Equation name is 'DATAOUT2', type is output
DATAOUT2 = _LC4_A1;
-- Node name is 'DATAOUT3'
-- Equation name is 'DATAOUT3', type is output
DATAOUT3 = _LC3_A1;
-- Node name is 'DATAOUT4'
-- Equation name is 'DATAOUT4', type is output
DATAOUT4 = _LC5_A3;
-- Node name is 'DATAOUT5'
-- Equation name is 'DATAOUT5', type is output
DATAOUT5 = _LC1_A2;
-- Node name is 'DATAOUT6'
-- Equation name is 'DATAOUT6', type is output
DATAOUT6 = _LC2_A6;
-- Node name is 'DATAOUT7'
-- Equation name is 'DATAOUT7', type is output
DATAOUT7 = _LC5_A5;
-- Node name is '~50~1'
-- Equation name is '~50~1', location is LC1_A7, type is buried.
-- synthesized logic cell
!_LC1_A7 = _LC1_A7~NOT;
_LC1_A7~NOT = LCELL( _EQ001);
_EQ001 = !ADDR0 & !ADDR1 & _LC2_A8;
-- Node name is '~71~1'
-- Equation name is '~71~1', location is LC2_A1, type is buried.
-- synthesized logic cell
!_LC2_A1 = _LC2_A1~NOT;
_LC2_A1~NOT = LCELL( _EQ002);
_EQ002 = ADDR0 & _LC2_A8;
-- Node name is ':71'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = LCELL( _EQ003);
_EQ003 = ADDR1 & !ADDR3 & !_LC2_A1;
-- Node name is '~78~1'
-- Equation name is '~78~1', location is LC2_A2, type is buried.
-- synthesized logic cell
!_LC2_A2 = _LC2_A2~NOT;
_LC2_A2~NOT = LCELL( _EQ004);
_EQ004 = !ADDR2
# CE;
-- Node name is ':78'
-- Equation name is '_LC5_A2', type is buried
!_LC5_A2 = _LC5_A2~NOT;
_LC5_A2~NOT = LCELL( _EQ005);
_EQ005 = !_LC2_A2
# ADDR1
# ADDR0
# ADDR3;
-- Node name is ':85'
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = LCELL( _EQ006);
_EQ006 = ADDR0 & !ADDR1 & !ADDR3 & _LC2_A2;
-- Node name is '~92~1'
-- Equation name is '~92~1', location is LC2_A8, type is buried.
-- synthesized logic cell
_LC2_A8 = LCELL( _EQ007);
_EQ007 = !ADDR2 & !CE;
-- Node name is '~99~1'
-- Equation name is '~99~1', location is LC6_A1, type is buried.
-- synthesized logic cell
_LC6_A1 = LCELL( _EQ008);
_EQ008 = !ADDR0 & ADDR1 & _LC2_A8;
-- Node name is ':153'
-- Equation name is '_LC6_A2', type is buried
_LC6_A2 = LCELL( _EQ009);
_EQ009 = _LC3_A2
# _LC5_A2;
-- Node name is '~179~1'
-- Equation name is '~179~1', location is LC1_A9, type is buried.
-- synthesized logic cell
_LC1_A9 = LCELL( _EQ010);
_EQ010 = ADDR3 & !_LC5_A1
# _LC1_A7 & !_LC5_A1;
-- Node name is '~179~2'
-- Equation name is '~179~2', location is LC8_A1, type is buried.
-- synthesized logic cell
!_LC8_A1 = _LC8_A1~NOT;
_LC8_A1~NOT = LCELL( _EQ011);
_EQ011 = !_LC1_A9
# _LC1_A1;
-- Node name is '~179~3'
-- Equation name is '~179~3', location is LC4_A2, type is buried.
-- synthesized logic cell
_LC4_A2 = LCELL( _EQ012);
_EQ012 = !ADDR0 & !ADDR1 & ADDR3 & _LC2_A2;
-- Node name is '~179~4'
-- Equation name is '~179~4', location is LC5_A5, type is buried.
-- synthesized logic cell
_LC5_A5 = LCELL( _EQ013);
_EQ013 = !_LC1_A1 & _LC1_A9 & _LC3_A2
# !_LC1_A1 & _LC1_A9 & _LC5_A2;
-- Node name is ':179'
-- Equation name is '_LC2_A6', type is buried
_LC2_A6 = LCELL( _EQ014);
_EQ014 = !_LC1_A1 & _LC1_A9 & _LC3_A2
# !_LC1_A1 & _LC1_A9 & _LC5_A2;
-- Node name is ':245'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = LCELL( _EQ015);
_EQ015 = _LC1_A9 & _LC6_A2
# _LC1_A1 & _LC1_A9
# _LC1_A9 & _LC4_A2;
-- Node name is '~278~1'
-- Equation name is '~278~1', location is LC2_A3, type is buried.
-- synthesized logic cell
_LC2_A3 = LCELL( _EQ016);
_EQ016 = ADDR1 & ADDR3 & _LC2_A8
# ADDR0 & ADDR3 & _LC2_A8;
-- Node name is '~278~2'
-- Equation name is '~278~2', location is LC1_A3, type is buried.
-- synthesized logic cell
_LC1_A3 = LCELL( _EQ017);
_EQ017 = !_LC1_A1 & _LC3_A2 & !_LC5_A2
# !_LC1_A1 & _LC2_A3 & !_LC5_A2;
-- Node name is ':278'
-- Equation name is '_LC5_A3', type is buried
_LC5_A3 = LCELL( _EQ018);
_EQ018 = ADDR3 & _LC1_A3
# _LC1_A3 & _LC1_A7
# ADDR3 & _LC5_A1
# _LC1_A7 & _LC5_A1;
-- Node name is ':309'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = LCELL( _EQ019);
_EQ019 = !_LC8_A1
# ADDR1 & ADDR3 & !_LC2_A1;
-- Node name is ':344'
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = LCELL( _EQ020);
_EQ020 = _LC1_A1 & _LC1_A9
# ADDR3 & _LC1_A9 & _LC6_A1;
-- Node name is ':372'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = LCELL( _EQ021);
_EQ021 = !ADDR1 & !ADDR3 & !_LC2_A1
# !ADDR3 & _LC6_A1;
-- Node name is ':377'
-- Equation name is '_LC1_A4', type is buried
_LC1_A4 = LCELL( _EQ022);
_EQ022 = ADDR3 & _LC5_A1
# _LC1_A7 & _LC5_A1;
-- Node name is ':408'
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = LCELL( _EQ023);
_EQ023 = !ADDR3 & _LC6_A1
# !ADDR3 & !_LC1_A7;
Project Information d:\lu\vhdl-digitallogic\disk\ch10\rom16_8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,361K
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