📄 sap1.rpt
字号:
- 1 - A 04 OR2 s 0 3 0 8 ~2413~1
- 1 - A 17 OR2 s 0 4 0 1 ~2437~1
- 1 - A 22 OR2 s 0 4 0 1 ~2449~1
- 2 - A 07 OR2 s 0 4 0 1 ~2461~1
- 3 - A 07 OR2 s 0 4 0 1 ~2473~1
- 3 - A 16 OR2 s 0 4 0 1 ~2485~1
- 3 - C 06 OR2 s 0 4 0 1 ~2497~1
- 4 - C 04 OR2 s 0 4 0 1 ~2509~1
- 5 - C 04 OR2 s 0 4 0 1 ~2521~1
- 1 - A 20 OR2 s 0 4 0 8 ~2521~2
- 1 - B 06 AND2 s 0 4 0 1 ~2533~1
- 5 - B 06 AND2 s ! 0 3 0 8 ~2629~1
- 3 - B 22 OR2 s 0 4 0 1 ~2641~1
- 3 - B 03 OR2 s 0 4 0 1 ~2653~1
- 1 - B 08 OR2 s 0 2 0 3 ~2665~1
- 3 - B 06 AND2 s ! 0 2 0 4 ~2665~2
- 4 - B 03 OR2 s 0 4 0 1 ~2665~3
- 7 - B 16 OR2 s 0 4 0 1 ~2677~1
- 1 - A 18 OR2 s 0 3 0 4 ~2683~1
- 1 - A 13 OR2 s 0 2 0 7 ~2689~1
- 8 - C 10 OR2 s 0 2 0 2 ~2689~2
- 1 - B 20 OR2 0 3 0 13 :2926
- 3 - C 20 AND2 0 2 0 5 :2928
- 5 - C 22 OR2 ! 0 2 0 1 :2934
- 1 - C 13 AND2 0 2 0 4 :2940
- 5 - C 21 AND2 0 2 0 5 :2946
- 4 - C 14 AND2 s 0 3 0 3 ~2960~1
- 3 - C 22 AND2 s 0 3 0 1 ~2960~2
- 5 - C 14 OR2 0 4 0 3 :2960
- 1 - C 14 OR2 0 4 0 3 :2972
- 4 - C 22 OR2 s 0 4 0 1 ~2978~1
- 3 - C 15 OR2 s 0 4 0 1 ~2978~2
- 1 - C 15 OR2 0 4 0 3 :2978
- 3 - C 14 OR2 0 3 0 3 :2990
- 2 - C 19 AND2 0 3 0 3 :2996
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch10\sap1.rpt
sap1a
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 24/ 96( 25%) 18/ 48( 37%) 6/ 48( 12%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 14/ 96( 14%) 4/ 48( 8%) 12/ 48( 25%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 11/ 96( 11%) 21/ 48( 43%) 15/ 48( 31%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch10\sap1.rpt
sap1a
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 61 CP
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch10\sap1.rpt
sap1a
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 18 RST
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch10\sap1.rpt
sap1a
** EQUATIONS **
CP : INPUT;
RST : INPUT;
-- Node name is ':22' = 'ACC0'
-- Equation name is 'ACC0', location is LC1_C4, type is buried.
ACC0 = DFFE( _EQ001, GLOBAL(!CP), GLOBAL(!RST), VCC, VCC);
_EQ001 = !_LC1_B17 & _LC5_C4
# ACC0 & _LC1_A20;
-- Node name is ':21' = 'ACC1'
-- Equation name is 'ACC1', location is LC2_C4, type is buried.
ACC1 = DFFE( _EQ002, GLOBAL(!CP), GLOBAL(!RST), VCC, VCC);
_EQ002 = !_LC1_B17 & _LC4_C4
# ACC1 & _LC1_A20;
-- Node name is ':20' = 'ACC2'
-- Equation name is 'ACC2', location is LC1_C6, type is buried.
ACC2 = DFFE( _EQ003, GLOBAL(!CP), GLOBAL(!RST), VCC, VCC);
_EQ003 = !_LC1_B17 & _LC3_C6
# ACC2 & _LC1_A20;
-- Node name is ':19' = 'ACC3'
-- Equation name is 'ACC3', location is LC1_A16, type is buried.
ACC3 = DFFE( _EQ004, GLOBAL(!CP), GLOBAL(!RST), VCC, VCC);
_EQ004 = !_LC1_B17 & _LC3_A16
# ACC3 & _LC1_A20;
-- Node name is ':18' = 'ACC4'
-- Equation name is 'ACC4', location is LC5_A7, type is buried.
ACC4 = DFFE( _EQ005, GLOBAL(!CP), GLOBAL(!RST), VCC, VCC);
_EQ005 = !_LC1_B17 & _LC3_A7
# ACC4 & _LC1_A20;
-- Node name is ':17' = 'ACC5'
-- Equation name is 'ACC5', location is LC1_A7, type is buried.
ACC5 = DFFE( _EQ006, GLOBAL(!CP), GLOBAL(!RST), VCC, VCC);
_EQ006 = !_LC1_B17 & _LC2_A7
# ACC5 & _LC1_A20;
-- Node name is ':16' = 'ACC6'
-- Equation name is 'ACC6', location is LC2_A22, type is buried.
ACC6 = DFFE( _EQ007, GLOBAL(!CP), GLOBAL(!RST), VCC, VCC);
_EQ007 = _LC1_A22 & !_LC1_B17
# ACC6 & _LC1_A20;
-- Node name is ':15' = 'ACC7'
-- Equation name is 'ACC7', location is LC3_A17, type is buried.
ACC7 = DFFE( _EQ008, GLOBAL(!CP), GLOBAL(!RST), VCC, VCC);
_EQ008 = _LC1_A17 & !_LC1_B17
# ACC7 & _LC1_A20;
-- Node name is ':69' = 'BReg0'
-- Equation name is 'BReg0', location is LC1_C7, type is buried.
BReg0 = DFFE( _EQ009, GLOBAL(!CP), VCC, VCC, !_LC1_B5);
_EQ009 = !_LC1_A4 & _LC2_C24
# BReg0 & _LC1_A4;
-- Node name is ':68' = 'BReg1'
-- Equation name is 'BReg1', location is LC1_C3, type is buried.
BReg1 = DFFE( _EQ010, GLOBAL(!CP), VCC, VCC, !_LC1_B5);
_EQ010 = !_LC1_A4 & _LC2_C19
# BReg1 & _LC1_A4;
-- Node name is ':67' = 'BReg2'
-- Equation name is 'BReg2', location is LC2_C8, type is buried.
BReg2 = DFFE( _EQ011, GLOBAL(!CP), VCC, VCC, !_LC1_B5);
_EQ011 = !_LC1_A4 & _LC3_C14
# BReg2 & _LC1_A4;
-- Node name is ':66' = 'BReg3'
-- Equation name is 'BReg3', location is LC3_A2, type is buried.
BReg3 = DFFE( _EQ012, GLOBAL(!CP), VCC, VCC, !_LC1_B5);
_EQ012 = !_LC1_A4 & _LC2_C15
# BReg3 & _LC1_A4;
-- Node name is ':65' = 'BReg4'
-- Equation name is 'BReg4', location is LC6_A10, type is buried.
BReg4 = DFFE( _EQ013, GLOBAL(!CP), VCC, VCC, !_LC1_B5);
_EQ013 = !_LC1_A4 & _LC1_C15
# BReg4 & _LC1_A4;
-- Node name is ':64' = 'BReg5'
-- Equation name is 'BReg5', location is LC2_A1, type is buried.
BReg5 = DFFE( _EQ014, GLOBAL(!CP), VCC, VCC, !_LC1_B5);
_EQ014 = !_LC1_A4 & _LC1_C14
# BReg5 & _LC1_A4;
-- Node name is ':63' = 'BReg6'
-- Equation name is 'BReg6', location is LC4_A4, type is buried.
BReg6 = DFFE( _EQ015, GLOBAL(!CP), VCC, VCC, !_LC1_B5);
_EQ015 = _LC3_A4
# BReg6 & _LC1_A4;
-- Node name is ':62' = 'BReg7'
-- Equation name is 'BReg7', location is LC2_A4, type is buried.
BReg7 = DFFE( _EQ016, GLOBAL(!CP), VCC, VCC, !_LC1_B5);
_EQ016 = BReg7 & _LC1_A4
# _LC3_A4;
-- Node name is ':93' = 'Flag'
-- Equation name is 'Flag', location is LC2_B19, type is buried.
!Flag = Flag~NOT;
Flag~NOT = DFFE( _EQ017, GLOBAL(!CP), GLOBAL(!RST), VCC, VCC);
_EQ017 = _LC1_B19 & _LC1_B21
# !Flag & !_LC1_B19
# !Flag & !_LC4_B15;
-- Node name is ':94' = 'F1'
-- Equation name is 'F1', location is LC2_C2, type is buried.
F1 = DFFE( _EQ018, GLOBAL(!CP), VCC, VCC, !_LC1_B5);
_EQ018 = F1 & _LC8_C10
# !_LC1_B8 & _LC8_C10;
-- Node name is ':49' = 'IR0'
-- Equation name is 'IR0', location is LC8_B16, type is buried.
IR0 = DFFE( _EQ019, GLOBAL(!CP), VCC, VCC, !_LC1_B5);
_EQ019 = IR0 & _LC2_B15
# !_LC2_B15 & _LC2_C24;
-- Node name is ':48' = 'IR1'
-- Equation name is 'IR1', location is LC5_B3, type is buried.
IR1 = DFFE( _EQ020, GLOBAL(!CP), VCC, VCC, !_LC1_B5);
_EQ020 = !_LC2_B15 & _LC2_C19
# IR1 & _LC2_B15;
-- Node name is ':47' = 'IR2'
-- Equation name is 'IR2', location is LC6_B3, type is buried.
IR2 = DFFE( _EQ021, GLOBAL(!CP), VCC, VCC, !_LC1_B5);
_EQ021 = !_LC2_B15 & _LC3_C14
# IR2 & _LC2_B15;
-- Node name is ':46' = 'IR3'
-- Equation name is 'IR3', location is LC8_B22, type is buried.
IR3 = DFFE( _EQ022, GLOBAL(!CP), VCC, VCC, !_LC1_B5);
_EQ022 = !_LC2_B15 & _LC2_C15
# IR3 & _LC2_B15;
-- Node name is ':45' = 'IR4'
-- Equation name is 'IR4', location is LC3_B5, type is buried.
IR4 = DFFE( _EQ023, GLOBAL(!CP), VCC, VCC, !_LC1_B5);
_EQ023 = _LC1_C15 & !_LC2_B15
# IR4 & _LC2_B15;
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