📄 counter60.rpt
字号:
- 5 - A 02 AND2 0 2 1 0 :125
- 3 - A 01 OR2 s 0 4 0 1 ~129~1
- 1 - A 01 OR2 ! 1 3 0 7 :136
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\counter60.rpt
counter60
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\counter60.rpt
counter60
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 7 CP
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\counter60.rpt
counter60
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 7 :136
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\counter60.rpt
counter60
** EQUATIONS **
CLR : INPUT;
CP : INPUT;
EC : INPUT;
S : INPUT;
-- Node name is 'BIN0'
-- Equation name is 'BIN0', type is output
BIN0 = TRI(Q0, GLOBAL( S));
-- Node name is 'BIN1'
-- Equation name is 'BIN1', type is output
BIN1 = TRI(Q1, GLOBAL( S));
-- Node name is 'BIN2'
-- Equation name is 'BIN2', type is output
BIN2 = TRI(Q2, GLOBAL( S));
-- Node name is 'BIN3'
-- Equation name is 'BIN3', type is output
BIN3 = TRI(Q3, GLOBAL( S));
-- Node name is 'BIN4'
-- Equation name is 'BIN4', type is output
BIN4 = TRI(Q4, GLOBAL( S));
-- Node name is 'BIN5'
-- Equation name is 'BIN5', type is output
BIN5 = TRI(Q5, GLOBAL( S));
-- Node name is 'CY60'
-- Equation name is 'CY60', type is output
CY60 = _LC5_A2;
-- Node name is ':19' = 'DLY'
-- Equation name is 'DLY', location is LC2_A2, type is buried.
DLY = DFFE( Q5, GLOBAL( CP), VCC, VCC, !_LC1_A1);
-- Node name is ':18' = 'Q0'
-- Equation name is 'Q0', location is LC1_A2, type is buried.
Q0 = DFFE( _EQ001, GLOBAL( CP), !_LC1_A1, VCC, VCC);
_EQ001 = !EC & Q0
# EC & !Q0;
-- Node name is ':17' = 'Q1'
-- Equation name is 'Q1', location is LC3_A3, type is buried.
Q1 = DFFE( _EQ002, GLOBAL( CP), !_LC1_A1, VCC, VCC);
_EQ002 = !Q0 & Q1
# EC & Q0 & !Q1
# !EC & Q1;
-- Node name is ':16' = 'Q2'
-- Equation name is 'Q2', location is LC4_A1, type is buried.
Q2 = DFFE( _EQ003, GLOBAL( CP), !_LC1_A1, VCC, VCC);
_EQ003 = !Q1 & Q2
# !Q0 & Q2
# EC & Q0 & Q1 & !Q2
# !EC & Q2;
-- Node name is ':15' = 'Q3'
-- Equation name is 'Q3', location is LC6_A1, type is buried.
Q3 = DFFE( _EQ004, GLOBAL( CP), !_LC1_A1, VCC, VCC);
_EQ004 = !_LC8_A1 & Q3
# EC & _LC8_A1 & !Q3
# !EC & Q3;
-- Node name is ':14' = 'Q4'
-- Equation name is 'Q4', location is LC7_A1, type is buried.
Q4 = DFFE( _EQ005, GLOBAL( CP), !_LC1_A1, VCC, VCC);
_EQ005 = !_LC5_A1 & Q4
# EC & _LC5_A1 & !Q4
# !EC & Q4;
-- Node name is ':13' = 'Q5'
-- Equation name is 'Q5', location is LC2_A1, type is buried.
Q5 = DFFE( _EQ006, GLOBAL( CP), !_LC1_A1, VCC, VCC);
_EQ006 = !Q4 & Q5
# !_LC5_A1 & Q5
# EC & _LC5_A1 & Q4 & !Q5
# !EC & Q5;
-- Node name is '|LPM_ADD_SUB:59|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = LCELL( _EQ007);
_EQ007 = Q0 & Q1 & Q2;
-- Node name is '|LPM_ADD_SUB:59|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = LCELL( _EQ008);
_EQ008 = Q0 & Q1 & Q2 & Q3;
-- Node name is ':125'
-- Equation name is '_LC5_A2', type is buried
_LC5_A2 = LCELL( _EQ009);
_EQ009 = DLY & !Q5;
-- Node name is '~129~1'
-- Equation name is '~129~1', location is LC3_A1, type is buried.
-- synthesized logic cell
_LC3_A1 = LCELL( _EQ010);
_EQ010 = !Q3
# !Q2
# Q1
# Q0;
-- Node name is ':136'
-- Equation name is '_LC1_A1', type is buried
!_LC1_A1 = _LC1_A1~NOT;
_LC1_A1~NOT = LCELL( _EQ011);
_EQ011 = !CLR & _LC3_A1
# !CLR & !Q5
# !CLR & !Q4;
Project Information d:\lu\vhdl-digitallogic\disk\ch7\counter60.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,448K
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