timer_set.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

--*************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--**************************************************************
ENTITY Timer_Set is
	PORT(
		 CP			: IN    STD_LOGIC;						-- CLOCK
		 SEGOUT		: OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);	-- SEG7 Display O/P
		 SELOUT		: OUT   STD_LOGIC_VECTOR(5 DOWNTO 0);	-- Select SEG7 O/P	
		 NUMOUT		: OUT   STD_LOGIC_VECTOR(3 DOWNTO 0);	-- Number Display Signal	
		 Key		: IN    STD_LOGIC_VECTOR(2 DOWNTO 0)  	-- Timer & Adjust & CLR
		);
END Timer_Set;

--**************************************************************
ARCHITECTURE a OF Timer_Set IS
	COMPONENT COUNTER60
		PORT(
			 	CP		: IN	STD_LOGIC;
			 	BIN		: OUT	STD_LOGIC_VECTOR (5 DOWNTO 0);
			 	S		: IN	STD_LOGIC;
				CLR		: IN 	STD_LOGIC;
				EC		: IN    STD_LOGIC;
				CY60	: OUT   STD_LOGIC
			);
	END COMPONENT;

	COMPONENT COUNTER24
		PORT(
			 	CP		: IN	STD_LOGIC;
			 	BIN		: OUT	STD_LOGIC_VECTOR (5 DOWNTO 0);
			 	S		: IN	STD_LOGIC;
				CLR		: IN 	STD_LOGIC;
				EC		: IN    STD_LOGIC;
				CY24	: OUT   STD_LOGIC
			);
	END COMPONENT;

	SIGNAL BIN 	: STD_LOGIC_VECTOR (5 DOWNTO 0);	--Binary O/P
	SIGNAL DBS 	: STD_LOGIC_VECTOR (5 DOWNTO 0);	--Binary Sec O/P
	SIGNAL DBM 	: STD_LOGIC_VECTOR (5 DOWNTO 0);	--Binary Min O/P
	SIGNAL DBH 	: STD_LOGIC_VECTOR (5 DOWNTO 0);	--Binary Hr O/P
	SIGNAL ENB 	: STD_LOGIC_VECTOR (2 DOWNTO 0);	--Enable Hr & Min & Sec O/P
	SIGNAL SEC	: STD_LOGIC;						--1 Hz 脉冲   
	SIGNAL BCD 	: STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL CLR	: STD_LOGIC;						--清除信号    
	SIGNAL CYS,CYM,CYH 		: STD_LOGIC;			--Sec