📄 debunce.rpt
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Total flipflops required: 22
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 7 8 7 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 7 8 7 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30/0
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\debunce.rpt
debuncea
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 0 CP
126 - - - -- INPUT 0 0 0 1 Key
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\debunce.rpt
debuncea
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
101 - - A -- OUTPUT 0 1 0 0 DIF_OUT
102 - - A -- OUTPUT 0 1 0 0 DLY_OUT
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\debunce.rpt
debuncea
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 03 AND2 0 3 0 4 |LPM_ADD_SUB:109|addcore:adder|:103
- 4 - A 04 AND2 0 4 0 4 |LPM_ADD_SUB:109|addcore:adder|:115
- 1 - A 04 AND2 0 4 0 4 |LPM_ADD_SUB:109|addcore:adder|:127
- 1 - A 01 AND2 0 4 0 3 |LPM_ADD_SUB:109|addcore:adder|:139
- 2 - A 03 DFFE + 0 3 0 7 Q14 (:5)
- 5 - A 03 DFFE + 0 2 0 1 Q13 (:6)
- 4 - A 03 DFFE + 0 1 0 2 Q12 (:7)
- 5 - A 01 DFFE + 0 3 0 1 Q11 (:8)
- 4 - A 01 DFFE + 0 2 0 2 Q10 (:9)
- 3 - A 01 DFFE + 0 1 0 3 Q9 (:10)
- 2 - A 04 DFFE + 0 3 0 1 Q8 (:11)
- 3 - A 04 DFFE + 0 2 0 2 Q7 (:12)
- 8 - A 04 DFFE + 0 1 0 3 Q6 (:13)
- 5 - A 04 DFFE + 0 3 0 1 Q5 (:14)
- 6 - A 04 DFFE + 0 2 0 2 Q4 (:15)
- 7 - A 04 DFFE + 0 1 0 3 Q3 (:16)
- 6 - A 03 DFFE + 0 2 0 1 Q2 (:17)
- 7 - A 03 DFFE + 0 1 0 2 Q1 (:18)
- 3 - A 03 DFFE + 0 0 0 3 Q0 (:19)
- 8 - A 02 DFFE + 0 1 0 6 D0 (:20)
- 2 - A 02 DFFE + 1 2 0 3 D0~38 (:22)
- 3 - A 02 DFFE + 0 3 0 2 D1 (:23)
- 4 - A 02 DFFE + 0 3 0 1 S (:24)
- 5 - A 02 DFFE + 0 3 0 1 R (:25)
- 6 - A 01 DFFE + 0 1 0 2 D0~54 (:28)
- 7 - A 01 DFFE + 0 1 0 1 D1~56 (:29)
- 6 - A 02 AND2 0 4 0 1 :194
- 7 - A 02 AND2 0 4 0 1 :200
- 1 - A 02 OR2 ! 0 2 1 1 :219
- 2 - A 01 AND2 0 2 1 0 :224
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\debunce.rpt
debuncea
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 6/ 48( 12%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\debunce.rpt
debuncea
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 22 CP
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\debunce.rpt
debuncea
** EQUATIONS **
CP : INPUT;
Key : INPUT;
-- Node name is 'DIF_OUT'
-- Equation name is 'DIF_OUT', type is output
DIF_OUT = _LC2_A1;
-- Node name is 'DLY_OUT'
-- Equation name is 'DLY_OUT', type is output
DLY_OUT = _LC1_A2;
-- Node name is ':22' = 'D0~38'
-- Equation name is 'D0~38', location is LC2_A2, type is buried.
D0~38 = DFFE( _EQ001, GLOBAL( CP), VCC, VCC, VCC);
_EQ001 = D0~38 & !Q14
# D0~38 & D0
# !D0 & Key & Q14;
-- Node name is ':28' = 'D0~54'
-- Equation name is 'D0~54', location is LC6_A1, type is buried.
D0~54 = DFFE( _LC1_A2, GLOBAL( CP), VCC, VCC, VCC);
-- Node name is ':20' = 'D0'
-- Equation name is 'D0', location is LC8_A2, type is buried.
D0 = DFFE( Q14, GLOBAL( CP), VCC, VCC, VCC);
-- Node name is ':29' = 'D1~56'
-- Equation name is 'D1~56', location is LC7_A1, type is buried.
D1~56 = DFFE( D0~54, GLOBAL( CP), VCC, VCC, VCC);
-- Node name is ':23' = 'D1'
-- Equation name is 'D1', location is LC3_A2, type is buried.
D1 = DFFE( _EQ002, GLOBAL( CP), VCC, VCC, VCC);
_EQ002 = D0~38 & !D0 & Q14
# D1 & !Q14
# D0 & D1;
-- Node name is ':19' = 'Q0'
-- Equation name is 'Q0', location is LC3_A3, type is buried.
Q0 = DFFE(!Q0, GLOBAL( CP), VCC, VCC, VCC);
-- Node name is ':18' = 'Q1'
-- Equation name is 'Q1', location is LC7_A3, type is buried.
Q1 = DFFE( _EQ003, GLOBAL( CP), VCC, VCC, VCC);
_EQ003 = Q0 & !Q1
# !Q0 & Q1;
-- Node name is ':17' = 'Q2'
-- Equation name is 'Q2', location is LC6_A3, type is buried.
Q2 = DFFE( _EQ004, GLOBAL( CP), VCC, VCC, VCC);
_EQ004 = !Q0 & Q2
# !Q1 & Q2
# Q0 & Q1 & !Q2;
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