📄 timer_set.rpt
字号:
- 2 - B 16 OR2 s 0 4 0 1 ~3751~2
- 6 - B 22 OR2 s 0 2 0 1 ~3790~1
- 2 - B 22 OR2 s 0 4 0 2 ~3790~2
- 1 - B 16 OR2 0 4 0 1 :3802
- 1 - C 17 AND2 s 0 2 0 1 ~3816~1
- 5 - B 22 OR2 0 3 0 1 :3835
- 3 - B 21 OR2 0 4 0 1 :3849
- 2 - B 21 OR2 0 4 0 1 :3859
- 1 - B 21 OR2 s 0 4 0 1 ~3861~1
- 4 - B 22 OR2 0 4 0 2 :3883
- 3 - B 22 OR2 0 4 0 1 :3900
- 2 - B 13 OR2 0 4 0 1 :3910
- 4 - B 13 OR2 s 0 2 0 1 ~3958~1
- 1 - B 15 OR2 0 4 0 1 :3958
- 1 - B 22 OR2 s 0 4 0 3 ~3997~1
- 5 - B 15 OR2 0 2 0 1 :3997
- 5 - B 13 OR2 s 0 4 0 1 ~4018~1
- 4 - B 16 OR2 0 4 0 2 :4033
- 6 - B 13 OR2 s 0 4 0 5 ~4054~1
- 3 - B 16 OR2 s 0 3 0 1 ~4054~2
- 7 - B 15 OR2 s 0 2 0 4 ~4063~1
- 3 - B 13 OR2 0 4 0 1 :4063
- 5 - C 21 OR2 ! 0 2 0 1 :4072
- 3 - C 03 OR2 ! 0 3 0 3 :4079
- 1 - C 19 OR2 ! 1 2 0 3 :4097
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\timer_set.rpt
timer_seta
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 16/ 96( 16%) 18/ 48( 37%) 9/ 48( 18%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 32/ 96( 33%) 27/ 48( 56%) 27/ 48( 56%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 24/ 96( 25%) 18/ 48( 37%) 24/ 48( 50%) 0/16( 0%) 10/16( 62%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\timer_set.rpt
timer_seta
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 52 CP
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\timer_set.rpt
timer_seta
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 7 |COUNTER60:U1|:136
LCELL 7 |COUNTER60:U2|:136
LCELL 5 |COUNTER24:U3|:120
LCELL 3 :4079
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\timer_set.rpt
timer_seta
** EQUATIONS **
CP : INPUT;
Key0 : INPUT;
Key1 : INPUT;
Key2 : INPUT;
-- Node name is ':167' = 'DLY'
-- Equation name is 'DLY', location is LC4_C20, type is buried.
DLY = DFFE( Q21, GLOBAL( CP), VCC, VCC, VCC);
-- Node name is ':194' = 'D0~208'
-- Equation name is 'D0~208', location is LC3_C19, type is buried.
D0~208 = DFFE( _LC5_C21, GLOBAL( CP), VCC, VCC, VCC);
-- Node name is ':187' = 'D0'
-- Equation name is 'D0', location is LC8_C21, type is buried.
D0 = DFFE( _EQ001, GLOBAL( CP), VCC, VCC, VCC);
_EQ001 = Key2 & Q14 & !SDLY
# D0 & !Q14
# D0 & SDLY;
-- Node name is ':195' = 'D1~210'
-- Equation name is 'D1~210', location is LC2_C19, type is buried.
D1~210 = DFFE( D0~208, GLOBAL( CP), VCC, VCC, VCC);
-- Node name is ':188' = 'D1'
-- Equation name is 'D1', location is LC7_C21, type is buried.
D1 = DFFE( _EQ002, GLOBAL( CP), VCC, VCC, VCC);
_EQ002 = D0 & Q14 & !SDLY
# D1 & !Q14
# D1 & SDLY;
-- Node name is 'NUMOUT0'
-- Equation name is 'NUMOUT0', type is output
NUMOUT0 = _LC4_B14;
-- Node name is 'NUMOUT1'
-- Equation name is 'NUMOUT1', type is output
NUMOUT1 = _LC4_B8;
-- Node name is 'NUMOUT2'
-- Equation name is 'NUMOUT2', type is output
NUMOUT2 = _LC5_B8;
-- Node name is 'NUMOUT3'
-- Equation name is 'NUMOUT3', type is output
NUMOUT3 = _LC2_B14;
-- Node name is ':200' = 'Q0~220'
-- Equation name is 'Q0~220', location is LC1_C3, type is buried.
!Q0~220 = Q0~220~NOT;
Q0~220~NOT = DFFE( _EQ003, GLOBAL( CP), !_LC3_C3, VCC, VCC);
_EQ003 = _LC1_C19 & Q0~220
# !_LC1_C19 & !Q0~220;
-- Node name is ':166' = 'Q0'
-- Equation name is 'Q0', location is LC4_A17, type is buried.
Q0 = DFFE(!Q0, GLOBAL( CP), VCC, VCC, VCC);
-- Node name is ':199' = 'Q1~220'
-- Equation name is 'Q1~220', location is LC2_C3, type is buried.
!Q1~220 = Q1~220~NOT;
Q1~220~NOT = DFFE( _EQ004, GLOBAL( CP), !_LC3_C3, VCC, VCC);
_EQ004 = Q0~220 & !Q1~220
# _LC1_C19 & !Q0~220 & Q1~220
# !_LC1_C19 & !Q1~220;
-- Node name is ':165' = 'Q1'
-- Equation name is 'Q1', location is LC2_A17, type is buried.
Q1 = DFFE( _EQ005, GLOBAL( CP), VCC, VCC, VCC);
_EQ005 = Q0 & !Q1
# !Q0 & Q1;
-- Node name is ':198' = 'Q2~220'
-- Equation name is 'Q2~220', location is LC4_C3, type is buried.
Q2~220 = DFFE( _EQ006, GLOBAL( CP), !_LC3_C3, VCC, VCC);
_EQ006 = Q1~220 & Q2~220
# Q0~220 & Q2~220
# _LC1_C19 & !Q0~220 & !Q1~220 & !Q2~220
# !_LC1_C19 & Q2~220;
-- Node name is ':164' = 'Q2'
-- Equation name is 'Q2', location is LC3_A17, type is buried.
Q2 = DFFE( _EQ007, GLOBAL( CP), VCC, VCC, VCC);
_EQ007 = !Q0 & Q2
# !Q1 & Q2
# Q0 & Q1 & !Q2;
-- Node name is ':163' = 'Q3'
-- Equation name is 'Q3', location is LC2_A15, type is buried.
Q3 = DFFE( _EQ008, GLOBAL( CP), VCC, VCC, VCC);
_EQ008 = !_LC1_A17 & Q3
# _LC1_A17 & !Q3;
-- Node name is ':162' = 'Q4'
-- Equation name is 'Q4', location is LC3_A15, type is buried.
Q4 = DFFE( _EQ009, GLOBAL( CP), VCC, VCC, VCC);
_EQ009 = !Q3 & Q4
# !_LC1_A17 & Q4
# _LC1_A17 & Q3 & !Q4;
-- Node name is ':161' = 'Q5'
-- Equation name is 'Q5', location is LC4_A15, type is buried.
Q5 = DFFE( _EQ010, GLOBAL( CP), VCC, VCC, VCC);
_EQ010 = !_LC7_A15 & Q5
# _LC7_A15 & !Q5;
-- Node name is ':160' = 'Q6'
-- Equation name is 'Q6', location is LC5_A15, type is buried.
Q6 = DFFE( _EQ011, GLOBAL( CP), VCC, VCC, VCC);
_EQ011 = !Q5 & Q6
# !_LC7_A15 & Q6
# _LC7_A15 & Q5 & !Q6;
-- Node name is ':159' = 'Q7'
-- Equation name is 'Q7', location is LC6_A15, type is buried.
Q7 = DFFE( _EQ012, GLOBAL( CP), VCC, VCC, VCC);
_EQ012 = !Q5 & Q7
# !_LC7_A15 & Q7
# !Q6 & Q7
# _LC7_A15 & Q5 & Q6 & !Q7;
-- Node name is ':158' = 'Q8'
-- Equation name is 'Q8', location is LC1_A20, type is buried.
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