ch3_3_1.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 39 行

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY CH3_3_1 is
	PORT(
			A,B								: IN	Std_Logic;
			Carry,Sum,Borrow,Difference		: OUT 	Std_Logic
		);
END CH3_3_1;

--*********************************************
ARCHITECTURE a OF CH3_3_1 IS
BEGIN

Half_Adder : Block			-- Half Adder
Begin
	Sum <= A Xor B;
	Carry <= A and B;
End Block Half_Adder;

Half_Subtractor: Block		-- Half Subtractor
Begin
	Difference <= A Xor B;
	Borrow <= Not A and B;	
End Block Half_Subtractor;

END a;