ch3_4_1.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 41 行

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY Altera;
USE Altera.maxplus2.all;

--*********************************************
ENTITY CH3_4_1 is
	PORT(
			Din,Clk,Clrn,Prn		: IN	Std_Logic;
			Q1,Q2,Q3,Q4				: OUT 	Std_Logic
		);
END CH3_4_1;

--*********************************************
ARCHITECTURE a OF CH3_4_1 IS
	Signal Di : Std_Logic_Vector(0 To 4);
BEGIN
	Di(0) <= Din;
	
	Shift_Gen: For I In 0 To 3 Generate
		Shift_D: Dff Port Map (d=>Di(I),CLK=>CLK,clrn=>Clrn,prn=>Prn,q=>Di(I+1));
	End Generate;

	Q1 <= Di(1);
	Q2 <= Di(2);
	Q3 <= Di(3);
	Q4 <= Di(4);

END a;