ch3_2_1.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY CH3_2_1 is
	PORT(
			D		: IN	Std_Logic_Vector(0 To 2);
			Z		: OUT 	Std_Logic_Vector(0 To 3)
		);
END CH3_2_1;

--*********************************************
ARCHITECTURE a OF CH3_2_1 IS
BEGIN
	Process(D)
		Variable Tmp : Std_Logic ;
	Begin
		Tmp := '0';
		For I In 0 to 2 Loop
			Tmp := Tmp XOR D(I);		
		End Loop;
		
		Z <= D & Tmp ;	

	End Process;


END a;