ch3_3_2.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 43 行

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch3_3_2 is
	PORT(
			A,B		: IN	Std_Logic_Vector(3 Downto 0);
			S		: OUT	Std_Logic_Vector(3 Downto 0);
			C		: INOUT	Std_Logic_Vector(4 Downto 0)
		);
END Ch3_3_2;

--*********************************************
ARCHITECTURE a OF Ch3_3_2 IS
	Component FullAdder
	Port (
		  	A		: IN	Std_Logic;
 			B		: IN	Std_Logic;
			C		: IN	Std_Logic;
			Carry	: OUT 	Std_Logic;
			Sum		: OUT 	Std_Logic
		 );
	End Component;	

BEGIN
	U0: Fulladder Port Map (A(0),B(0),C(0),C(1),S(0));	
	U1: Fulladder Port Map (A(1),B(1),C(1),C(2),S(1));	
	U2: Fulladder Port Map (A(2),B(2),C(2),C(3),S(2));	
	U3: Fulladder Port Map (A(3),B(3),C(3),C(4),S(3));	

	C(0) <= '0';
END a;