keyboard_dec.rpt

《VHDL与数字电路设计》配套光盘,可以实际调用

        | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC22 -> * - - - - - - - - - - - - | - * | <-- out_func1
LC21 -> * - - - - - - - - - - - - | - * | <-- out_func2
LC25 -> * - - - - - - - - - - - - | - * | <-- out_func3
LC24 -> * - - - - - - - - - - - - | - * | <-- out_func4
LC17 -> * - - - - - - - - - - - - | - * | <-- out_func5
LC18 -> * - - - - - - - - - - - - | - * | <-- out_func6
LC20 -> - * - - - - - - - - - - - | - * | <-- out_numb1
LC23 -> - * - - - - - - - - - - - | - * | <-- out_numb2
LC19 -> - * - - - - - - - - - - - | - * | <-- out_numb3

Pin
43   -> - - - - - - - - - - - - - | - - | <-- clk
9    -> - - * * * * * * * * * * - | - * | <-- clk_CNTB0
8    -> - - * * * * * * * * * * * | - * | <-- clk_CNTB1
7    -> - - * * * * * * * * * * * | - * | <-- key_in0
6    -> - - * * * * * * * * * * * | - * | <-- key_in1
5    -> - - * * * * * * * * * * * | - * | <-- key_in2
4    -> - - * * * * * * * * * * * | - * | <-- key_in3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                 c:\vhdl\disk\ch8\keyboard_dec.rpt
keyboard_dec

** EQUATIONS **

clk      : INPUT;
clk_CNTB0 : INPUT;
clk_CNTB1 : INPUT;
key_in0  : INPUT;
key_in1  : INPUT;
key_in2  : INPUT;
key_in3  : INPUT;

-- Node name is 'flag_func' 
-- Equation name is 'flag_func', location is LC027, type is output.
 flag_func = LCELL( _EQ001 $  VCC);
  _EQ001 = !out_func1 & !out_func2 & !out_func3 & !out_func4 & !out_func5 & 
             !out_func6;

-- Node name is 'flag_numb' 
-- Equation name is 'flag_numb', location is LC028, type is output.
 flag_numb = LCELL( _EQ002 $ !out_numb3);
  _EQ002 = !out_numb1 & !out_numb2 &  out_numb3;

-- Node name is 'out_func0' = 'T0' 
-- Equation name is 'out_func0', location is LC026, type is output.
 out_func0 = DFFE( _EQ003 $  VCC, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 =  clk_CNTB0 &  clk_CNTB1 &  key_in0 &  key_in1 & !key_in2 & 
              key_in3
         #  clk_CNTB0 &  clk_CNTB1 &  key_in0 &  key_in1 &  key_in2 & 
             !key_in3
         #  clk_CNTB1 & !key_in0 &  key_in1 &  key_in2 &  key_in3
         #  clk_CNTB1 &  key_in0 & !key_in1 &  key_in2 &  key_in3;

-- Node name is 'out_func1' = 'T1' 
-- Equation name is 'out_func1', location is LC022, type is output.
 out_func1 = DFFE( _EQ004 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 = !clk_CNTB0 &  clk_CNTB1 &  key_in0 & !key_in1 &  key_in2 & 
              key_in3;

-- Node name is 'out_func2' = 'T2' 
-- Equation name is 'out_func2', location is LC021, type is output.
 out_func2 = DFFE( _EQ005 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 = !clk_CNTB0 &  clk_CNTB1 & !key_in0 &  key_in1 &  key_in2 & 
              key_in3;

-- Node name is 'out_func3' = 'T3' 
-- Equation name is 'out_func3', location is LC025, type is output.
 out_func3 = DFFE( _EQ006 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 =  clk_CNTB0 &  clk_CNTB1 &  key_in0 &  key_in1 &  key_in2 & 
             !key_in3;

-- Node name is 'out_func4' = 'T4' 
-- Equation name is 'out_func4', location is LC024, type is output.
 out_func4 = DFFE( _EQ007 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 =  clk_CNTB0 &  clk_CNTB1 &  key_in0 &  key_in1 & !key_in2 & 
              key_in3;

-- Node name is 'out_func5' = 'T5' 
-- Equation name is 'out_func5', location is LC017, type is output.
 out_func5 = DFFE( _EQ008 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 =  clk_CNTB0 &  clk_CNTB1 &  key_in0 & !key_in1 &  key_in2 & 
              key_in3;

-- Node name is 'out_func6' = 'T6' 
-- Equation name is 'out_func6', location is LC018, type is output.
 out_func6 = DFFE( _EQ009 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 =  clk_CNTB0 &  clk_CNTB1 & !key_in0 &  key_in1 &  key_in2 & 
              key_in3;

-- Node name is 'out_numb0' = 'F0' 
-- Equation name is 'out_numb0', location is LC029, type is output.
 out_numb0 = DFFE( _EQ010 $  VCC, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 =  clk_CNTB0 & !clk_CNTB1 &  key_in0 &  key_in1 &  key_in2 & 
             !key_in3
         # !clk_CNTB1 &  key_in0 & !key_in1 &  key_in2 &  key_in3
         # !clk_CNTB0 &  key_in0 &  key_in1 &  key_in2 & !key_in3;

-- Node name is 'out_numb1' = 'F1' 
-- Equation name is 'out_numb1', location is LC020, type is output.
 out_numb1 = DFFE( _EQ011 $  VCC, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 =  clk_CNTB0 & !clk_CNTB1 &  key_in0 &  key_in1 & !key_in2 & 
              key_in3
         #  clk_CNTB0 & !clk_CNTB1 &  key_in0 &  key_in1 &  key_in2 & 
             !key_in3
         # !clk_CNTB0 &  key_in0 &  key_in1 & !key_in2 &  key_in3
         # !clk_CNTB0 &  key_in0 &  key_in1 &  key_in2 & !key_in3;

-- Node name is 'out_numb2' = 'F2' 
-- Equation name is 'out_numb2', location is LC023, type is output.
 out_numb2 = DFFE( _EQ012 $  VCC, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ012 = !clk_CNTB0 & !clk_CNTB1 & !key_in0 &  key_in1 &  key_in2 & 
              key_in3
         # !clk_CNTB0 & !clk_CNTB1 &  key_in0 & !key_in1 &  key_in2 & 
              key_in3
         # !clk_CNTB0 &  key_in0 &  key_in1 & !key_in2 &  key_in3
         # !clk_CNTB0 &  key_in0 &  key_in1 &  key_in2 & !key_in3;

-- Node name is 'out_numb3' = 'F3' 
-- Equation name is 'out_numb3', location is LC019, type is output.
 out_numb3 = DFFE( _EQ013 $  VCC, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ013 = !clk_CNTB1 & !key_in0 &  key_in1 &  key_in2 &  key_in3
         # !clk_CNTB1 &  key_in0 & !key_in1 &  key_in2 &  key_in3
         # !clk_CNTB1 &  key_in0 &  key_in1 & !key_in2 &  key_in3
         # !clk_CNTB1 &  key_in0 &  key_in1 &  key_in2 & !key_in3;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                          c:\vhdl\disk\ch8\keyboard_dec.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,456K