📄 elec_lock.rpt
字号:
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\vhdl\disk\ch8\elec_lock.rpt
elec_lockcq
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
81 - - C -- OUTPUT 0 1 0 0 BCD_CODE0
83 - - C -- OUTPUT 0 1 0 0 BCD_CODE1
78 - - C -- OUTPUT 0 1 0 0 BCD_CODE2
79 - - C -- OUTPUT 0 1 0 0 BCD_CODE3
14 - - A -- OUTPUT 0 1 0 0 BCD_CODE4
12 - - A -- OUTPUT 0 1 0 0 BCD_CODE5
13 - - A -- OUTPUT 0 1 0 0 BCD_CODE6
109 - - - 01 OUTPUT 0 1 0 0 BCD_CODE7
10 - - A -- OUTPUT 0 1 0 0 BCD_CODE8
102 - - A -- OUTPUT 0 1 0 0 BCD_CODE9
9 - - A -- OUTPUT 0 1 0 0 BCD_CODE10
98 - - A -- OUTPUT 0 1 0 0 BCD_CODE11
11 - - A -- OUTPUT 0 1 0 0 BCD_CODE12
99 - - A -- OUTPUT 0 1 0 0 BCD_CODE13
8 - - A -- OUTPUT 0 1 0 0 BCD_CODE14
96 - - A -- OUTPUT 0 1 0 0 BCD_CODE15
114 - - - 04 OUTPUT 0 1 0 0 CLEAR
82 - - C -- OUTPUT 0 1 0 0 CLK_SCAN0
39 - - - 21 OUTPUT 0 1 0 0 CLK_SCAN1
80 - - C -- OUTPUT 0 1 0 0 CLK_SCAN2
32 - - C -- OUTPUT 0 1 0 0 CLK_SCAN3
7 - - A -- OUTPUT 0 1 0 0 ENLOCK
86 - - B -- OUTPUT 0 1 0 0 FLAG_FUNC
111 - - - 02 OUTPUT 0 1 0 0 FLAG_NUMB
100 - - A -- OUTPUT 0 0 0 0 LED_COM
101 - - A -- OUTPUT 0 1 0 0 NUMB_CNT0
95 - - A -- OUTPUT 0 1 0 0 NUMB_CNT1
97 - - A -- OUTPUT 0 1 0 0 NUMB_CNT2
23 - - B -- OUTPUT 0 1 0 0 SEGOUT0
26 - - C -- OUTPUT 0 1 0 0 SEGOUT1
27 - - C -- OUTPUT 0 1 0 0 SEGOUT2
28 - - C -- OUTPUT 0 1 0 0 SEGOUT3
29 - - C -- OUTPUT 0 1 0 0 SEGOUT4
30 - - C -- OUTPUT 0 1 0 0 SEGOUT5
31 - - C -- OUTPUT 0 1 0 0 SEGOUT6
33 - - C -- OUTPUT 0 1 0 0 SELOUT0
36 - - - 24 OUTPUT 0 1 0 0 SELOUT1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\vhdl\disk\ch8\elec_lock.rpt
elec_lockcq
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - B 05 DFFE 1 1 0 1 |debouncing:U1|dff1
- 6 - B 05 DFFE 0 2 0 1 |debouncing:U1|dff2
- 5 - B 05 DFFE 0 2 0 4 |debouncing:U1|d0 (|debouncing:U1|:13)
- 2 - B 05 DFFE 0 2 0 3 |debouncing:U1|d1 (|debouncing:U1|:14)
- 5 - B 10 DFFE 1 1 0 1 |debouncing:U2|dff1
- 4 - B 10 DFFE 0 2 0 1 |debouncing:U2|dff2
- 2 - B 10 DFFE 0 2 0 4 |debouncing:U2|d0 (|debouncing:U2|:13)
- 4 - B 11 DFFE 0 2 0 3 |debouncing:U2|d1 (|debouncing:U2|:14)
- 3 - B 11 DFFE 1 1 0 1 |debouncing:U3|dff1
- 5 - B 11 DFFE 0 2 0 1 |debouncing:U3|dff2
- 7 - B 11 DFFE 0 2 0 4 |debouncing:U3|d0 (|debouncing:U3|:13)
- 8 - B 11 DFFE 0 2 0 3 |debouncing:U3|d1 (|debouncing:U3|:14)
- 1 - A 16 AND2 0 3 0 3 |LPM_ADD_SUB:238|addcore:adder|:135
- 1 - C 23 DFFE + 0 3 1 8 Q5 (:59)
- 8 - C 23 DFFE + 0 2 1 9 Q4 (:60)
- 2 - C 23 DFFE + 0 1 0 2 Q3 (:61)
- 2 - A 16 DFFE + 0 2 0 1 Q2 (:62)
- 3 - A 16 DFFE + 0 1 0 2 Q1 (:63)
- 3 - B 17 DFFE + 0 0 0 42 Q0 (:64)
- 6 - C 12 DFFE 0 5 0 2 N3 (:97)
- 5 - C 12 DFFE 0 5 0 2 N2 (:98)
- 1 - C 12 DFFE 0 5 0 2 N1 (:99)
- 1 - B 10 DFFE 0 5 0 2 N0 (:100)
- 3 - B 04 DFFE 0 4 0 1 F3 (:101)
- 3 - B 09 DFFE 0 3 0 19 F2 (:102)
- 2 - B 04 DFFE 0 3 0 3 F0 (:104)
- 4 - B 04 DFFE 0 2 0 2 R0 (:105)
- 5 - B 04 DFFE 0 2 0 1 R1 (:106)
- 7 - A 09 DFFE 0 4 1 6 ACC15 (:111)
- 2 - A 07 DFFE 0 4 1 6 ACC14 (:112)
- 4 - A 03 DFFE 0 4 1 6 ACC13 (:113)
- 5 - A 03 DFFE 0 4 1 5 ACC12 (:114)
- 5 - A 11 DFFE 0 4 1 7 ACC11 (:115)
- 3 - A 03 DFFE 0 4 1 7 ACC10 (:116)
- 1 - A 08 DFFE 0 4 1 7 ACC9 (:117)
- 4 - A 05 DFFE 0 4 1 6 ACC8 (:118)
- 2 - C 01 DFFE 0 4 1 5 ACC7 (:119)
- 7 - A 12 DFFE 0 4 1 5 ACC6 (:120)
- 6 - A 06 DFFE 0 4 1 7 ACC5 (:121)
- 8 - A 10 DFFE 0 4 1 8 ACC4 (:122)
- 5 - C 01 DFFE 0 4 1 6 ACC3 (:123)
- 7 - C 01 DFFE 0 4 1 6 ACC2 (:124)
- 1 - C 01 DFFE 0 4 1 6 ACC1 (:125)
- 3 - C 01 DFFE 0 4 1 6 ACC0 (:126)
- 5 - A 02 DFFE 0 4 1 19 NC2 (:127)
- 7 - A 02 DFFE 0 4 1 2 NC1 (:128)
- 1 - A 02 DFFE 0 3 1 3 NC0 (:129)
- 8 - A 20 DFFE 0 4 0 1 REG15 (:131)
- 2 - B 24 DFFE 0 4 0 1 REG14 (:132)
- 3 - B 24 DFFE 0 4 0 1 REG13 (:133)
- 3 - A 04 DFFE 0 4 0 1 REG12 (:134)
- 4 - A 04 DFFE 0 4 0 1 REG11 (:135)
- 4 - A 21 DFFE 0 4 0 1 REG10 (:136)
- 5 - A 21 DFFE 0 4 0 1 REG9 (:137)
- 2 - A 02 DFFE 0 4 0 1 REG8 (:138)
- 6 - A 04 DFFE 0 4 0 1 REG7 (:139)
- 7 - B 24 DFFE 0 4 0 1 REG6 (:140)
- 6 - A 02 DFFE 0 4 0 1 REG5 (:141)
- 2 - A 04 DFFE 0 4 0 1 REG4 (:142)
- 1 - B 24 DFFE 0 4 0 1 REG3 (:143)
- 1 - A 21 DFFE 0 4 0 1 REG2 (:144)
- 3 - A 21 DFFE 0 4 0 1 REG1 (:145)
- 4 - A 20 DFFE 0 4 0 1 REG0 (:146)
- 6 - A 20 DFFE 0 4 0 1 QA (:147)
- 7 - A 20 DFFE 0 4 0 1 QB (:148)
- 6 - B 11 OR2 s 0 4 0 1 ~601~1
- 4 - B 05 OR2 s 0 3 0 8 ~601~2
- 3 - B 10 OR2 ! 0 2 0 1 :601
- 8 - C 12 OR2 s ! 0 4 0 2 ~606~1
- 7 - C 12 OR2 s 0 3 0 3 ~606~2
- 4 - C 12 OR2 s 0 3 0 3 ~625~1
- 3 - C 12 OR2 s 0 4 0 3 ~639~1
- 2 - C 12 OR2 0 4 0 2 :652
- 8 - B 10 OR2 0 4 0 1 :690
- 7 - B 10 OR2 0 4 0 1 :696
- 6 - B 10 OR2 0 4 0 1 :702
- 1 - B 11 OR2 s 0 4 0 1 ~785~1
- 3 - B 05 AND2 s 0 3 0 7 ~785~2
- 2 - B 11 OR2 s 0 4 0 1 ~799~1
- 1 - B 05 OR2 s 0 3 0 7 ~799~2
- 1 - B 04 OR2 ! 0 2 1 19 :921
- 4 - A 02 AND2 0 3 0 19 :1542
- 8 - A 24 OR2 s ! 0 3 0 1 ~1601~1
- 7 - A 24 OR2 s ! 0 3 0 1 ~1601~2
- 6 - A 24 OR2 s ! 0 4 0 1 ~1601~3
- 5 - A 24 OR2 s ! 0 4 0 1 ~1601~4
- 4 - A 24 OR2 s ! 0 3 0 2 ~1601~5
- 1 - A 24 OR2 ! 0 4 0 2 :1601
- 1 - A 04 OR2 s ! 0 4 0 1 ~1753~1
- 3 - A 02 OR2 s ! 0 4 0 1 ~1753~2
- 8 - A 21 OR2 s ! 0 4 0 1 ~1753~3
- 5 - A 20 OR2 s ! 0 4 0 1 ~1753~4
- 7 - A 21 OR2 s ! 0 3 0 1 ~1753~5
- 6 - A 21 OR2 s ! 0 4 0 1 ~1753~6
- 6 - B 24 OR2 s ! 0 4 0 1 ~1753~7
- 5 - A 04 OR2 s ! 0 4 0 1 ~1753~8
- 5 - B 24 OR2 s ! 0 4 0 1 ~1753~9
- 4 - B 24 OR2 s ! 0 3 0 1 ~1753~10
- 2 - A 21 OR2 ! 0 4 0 2 :1753
- 2 - A 20 OR2 s 0 4 0 1 ~2151~1
- 3 - A 20 OR2 s 0 3 0 1 ~2157~1
- 2 - C 15 AND2 0 2 1 12 :2192
- 7 - C 22 OR2 ! 0 2 1 10 :2195
- 4 - C 21 OR2 ! 0 2 1 9 :2198
- 7 - C 19 OR2 0 4 1 0 :2222
- 6 - C 01 OR2 ! 0 4 1 19 :2314
- 7 - B 04 OR2 0 3 1 1 :2356
- 3 - C 20 AND2 0 2 0 10 :2371
- 8 - C 01 OR2 0 4 0 1 :2421
- 4 - C 01 OR2 0 3 0 1 :2427
- 2 - C 13 OR2 0 3 0 4 :2433
- 6 - B 14 OR2 ! 0 4 0 1 :2442
- 5 - B 14 OR2 ! 0 3 0 1 :2445
- 1 - B 14 OR2 ! 0 3 0 9 :2448
- 4 - B 14 OR2 0 4 0 1 :2457
- 2 - B 14 OR2 0 3 0 1 :2460
- 3 - B 14 OR2 0 3 0 9 :2463
- 4 - C 24 OR2 0 4 0 1 :2472
- 1 - C 24 OR2 0 3 0 1 :2475
- 3 - C 24 OR2 0 3 0 4 :2478
- 2 - B 16 OR2 s 0 2 0 3 ~2496~1
- 1 - C 13 OR2 s 0 2 0 8 ~2501~1
- 2 - C 17 AND2 s ! 0 2 0 1 ~2501~2
- 1 - C 14 OR2 ! 0 3 1 0 :2501
- 1 - B 16 OR2 ! 0 3 0 1 :2511
- 6 - C 13 OR2 s 0 2 0 6 ~2526~1
- 1 - C 17 OR2 ! 0 3 0 2 :2526
- 6 - C 17 OR2 0 4 1 0 :2606
- 5 - C 13 OR2 0 4 1 0 :2637
- 3 - C 06 OR2 s 0 4 0 1 ~2670~1
- 2 - C 06 OR2 s 0 3 0 1 ~2670~2
- 1 - C 06 OR2 s 0 4 0 1 ~2670~3
- 3 - A 24 OR2 s 0 3 0 1 ~2670~4
- 2 - A 24 OR2 s 0 4 0 1 ~2670~5
- 1 - C 20 OR2 s 0 4 0 1 ~2670~6
- 2 - C 20 OR2 s 0 4 0 1 ~2670~7
- 5 - C 24 OR2 s 0 4 0 1 ~2670~8
- 6 - C 24 OR2 s 0 4 0 1 ~2670~9
- 7 - C 24 OR2 s 0 4 0 1 ~2670~10
- 8 - C 24 OR2 s 0 4 0 1 ~2670~11
- 2 - C 24 OR2 s 0 4 0 1 ~2670~12
- 3 - C 17 OR2 s 0 4 0 1 ~2670~13
- 5 - C 17 OR2 s 0 4 0 1 ~2670~14
- 7 - C 17 OR2 s 0 4 0 1 ~2670~15
- 4 - C 17 OR2 0 4 1 0 :2670
- 3 - C 13 OR2 0 4 1 0 :2703
- 1 - C 16 OR2 0 4 1 0 :2769
- 6 - B 16 OR2 0 4 1 0 :2802
- 1 - A 20 AND2 0 2 1 0 :2845
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\vhdl\disk\ch8\elec_lock.rpt
elec_lockcq
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 22/ 96( 22%) 5/ 48( 10%) 6/ 48( 12%) 0/16( 0%) 16/16(100%) 0/16( 0%)
B: 20/ 96( 20%) 8/ 48( 16%) 5/ 48( 10%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 18/ 96( 18%) 12/ 48( 25%) 19/ 48( 39%) 0/16( 0%) 14/16( 87%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\vhdl\disk\ch8\elec_lock.rpt
elec_lockcq
** CLOCK SIGNALS **
Type Fan-out Name
DFF 43 Q0
LCELL 20 :2314
INPUT 6 CLK_4M
Device-Specific Information: c:\vhdl\disk\ch8\elec_lock.rpt
elec_lockcq
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