📄 ctrl.rpt
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_EQ080 = BCD_CODE3 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & !REG3
# !BCD_CODE3 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & REG3;
-- Node name is ':132' = 'REG4'
-- Equation name is 'REG4', location is LC076, type is buried.
REG4 = TFFE( _EQ081, Q0, VCC, VCC, VCC);
_EQ081 = BCD_CODE4 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & !REG4
# !BCD_CODE4 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & REG4;
-- Node name is ':131' = 'REG5'
-- Equation name is 'REG5', location is LC075, type is buried.
REG5 = TFFE( _EQ082, Q0, VCC, VCC, VCC);
_EQ082 = BCD_CODE5 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & !REG5
# !BCD_CODE5 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & REG5;
-- Node name is ':130' = 'REG6'
-- Equation name is 'REG6', location is LC074, type is buried.
REG6 = TFFE( _EQ083, Q0, VCC, VCC, VCC);
_EQ083 = BCD_CODE6 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & !REG6
# !BCD_CODE6 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & REG6;
-- Node name is ':129' = 'REG7'
-- Equation name is 'REG7', location is LC065, type is buried.
REG7 = TFFE( _EQ084, Q0, VCC, VCC, VCC);
_EQ084 = BCD_CODE7 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & !REG7
# !BCD_CODE7 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & REG7;
-- Node name is ':128' = 'REG8'
-- Equation name is 'REG8', location is LC073, type is buried.
REG8 = TFFE( _EQ085, Q0, VCC, VCC, VCC);
_EQ085 = BCD_CODE8 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & !REG8
# !BCD_CODE8 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & REG8;
-- Node name is ':127' = 'REG9'
-- Equation name is 'REG9', location is LC087, type is buried.
REG9 = TFFE( _EQ086, Q0, VCC, VCC, VCC);
_EQ086 = BCD_CODE9 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & !REG9
# !BCD_CODE9 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & REG9;
-- Node name is ':126' = 'REG10'
-- Equation name is 'REG10', location is LC094, type is buried.
REG10 = TFFE( _EQ087, Q0, VCC, VCC, VCC);
_EQ087 = BCD_CODE10 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & !REG10
# !BCD_CODE10 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & REG10;
-- Node name is ':125' = 'REG11'
-- Equation name is 'REG11', location is LC095, type is buried.
REG11 = TFFE( _EQ088, Q0, VCC, VCC, VCC);
_EQ088 = BCD_CODE11 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & !REG11
# !BCD_CODE11 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & REG11;
-- Node name is ':124' = 'REG12'
-- Equation name is 'REG12', location is LC090, type is buried.
REG12 = TFFE( _EQ089, Q0, VCC, VCC, VCC);
_EQ089 = BCD_CODE12 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & !REG12
# !BCD_CODE12 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & REG12;
-- Node name is ':123' = 'REG13'
-- Equation name is 'REG13', location is LC082, type is buried.
REG13 = TFFE( _EQ090, Q0, VCC, VCC, VCC);
_EQ090 = BCD_CODE13 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & !REG13
# !BCD_CODE13 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & REG13;
-- Node name is ':122' = 'REG14'
-- Equation name is 'REG14', location is LC092, type is buried.
REG14 = TFFE( _EQ091, Q0, VCC, VCC, VCC);
_EQ091 = BCD_CODE14 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & !REG14
# !BCD_CODE14 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & REG14;
-- Node name is ':121' = 'REG15'
-- Equation name is 'REG15', location is LC091, type is buried.
REG15 = TFFE( _EQ092, Q0, VCC, VCC, VCC);
_EQ092 = BCD_CODE15 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & !REG15
# !BCD_CODE15 & F2 & !NUMB_CNT0 & !NUMB_CNT1 & NUMB_CNT2 & REG15;
-- Node name is ':95' = 'R0'
-- Equation name is 'R0', location is LC085, type is buried.
R0 = DFFE( _EQ093 $ F2, Q0, VCC, VCC, VCC);
_EQ093 = F0 & !F2;
-- Node name is ':96' = 'R1'
-- Equation name is 'R1', location is LC034, type is buried.
R1 = DFFE( R0 $ GND, Q0, VCC, VCC, VCC);
-- Node name is '|debouncing:U1|dff1'
-- Equation name is '_LC048', type is buried
_LC048 = DFFE( GND $ VCC, Q0, !KEY_IN0, VCC, VCC);
-- Node name is '|debouncing:U1|dff2'
-- Equation name is '_LC047', type is buried
_LC047 = DFFE( GND $ VCC, Q0, _LC048, VCC, VCC);
-- Node name is '|debouncing:U1|:13' = '|debouncing:U1|d0'
-- Equation name is '_LC046', type is buried
_LC046 = DFFE(!_LC047 $ GND, Q0, VCC, VCC, VCC);
-- Node name is '|debouncing:U1|:14' = '|debouncing:U1|d1'
-- Equation name is '_LC060', type is buried
_LC060 = DFFE( _LC046 $ GND, Q0, VCC, VCC, VCC);
-- Node name is '|debouncing:U2|dff1'
-- Equation name is '_LC039', type is buried
_LC039 = DFFE( GND $ VCC, Q0, !KEY_IN1, VCC, VCC);
-- Node name is '|debouncing:U2|dff2'
-- Equation name is '_LC038', type is buried
_LC038 = DFFE( GND $ VCC, Q0, _LC039, VCC, VCC);
-- Node name is '|debouncing:U2|:13' = '|debouncing:U2|d0'
-- Equation name is '_LC036', type is buried
_LC036 = DFFE(!_LC038 $ GND, Q0, VCC, VCC, VCC);
-- Node name is '|debouncing:U2|:14' = '|debouncing:U2|d1'
-- Equation name is '_LC063', type is buried
_LC063 = DFFE( _LC036 $ GND, Q0, VCC, VCC, VCC);
-- Node name is '|debouncing:U3|dff1'
-- Equation name is '_LC020', type is buried
_LC020 = DFFE( GND $ VCC, Q0, !KEY_IN2, VCC, VCC);
-- Node name is '|debouncing:U3|dff2'
-- Equation name is '_LC044', type is buried
_LC044 = DFFE( GND $ VCC, Q0, _LC020, VCC, VCC);
-- Node name is '|debouncing:U3|:13' = '|debouncing:U3|d0'
-- Equation name is '_LC022', type is buried
_LC022 = DFFE(!_LC044 $ GND, Q0, VCC, VCC, VCC);
-- Node name is '|debouncing:U3|:14' = '|debouncing:U3|d1'
-- Equation name is '_LC062', type is buried
_LC062 = DFFE( _LC022 $ GND, Q0, VCC, VCC, VCC);
-- Node name is '~1762~1'
-- Equation name is '~1762~1', location is LC086, type is buried.
-- synthesized logic cell
_LC086 = LCELL( _EQ094 $ _EQ095);
_EQ094 = !BCD_CODE0 & !_LC030 & !_LC066 & !_LC078 & REG0 & _X008 & _X009 &
_X010 & _X011 & _X012 & _X013 & _X014 & _X015 & _X016 &
_X017 & _X018 & _X019 & _X020
# BCD_CODE0 & !_LC030 & !_LC066 & !_LC078 & !REG0 & _X008 & _X009 &
_X010 & _X011 & _X012 & _X013 & _X014 & _X015 & _X016 &
_X017 & _X018 & _X019 & _X020
# !BCD_CODE1 & !_LC030 & !_LC066 & !_LC078 & REG1 & _X008 & _X009 &
_X010 & _X011 & _X012 & _X013 & _X014 & _X015 & _X016 &
_X017 & _X018 & _X019 & _X020
# BCD_CODE1 & !_LC030 & !_LC066 & !_LC078 & !REG1 & _X008 & _X009 &
_X010 & _X011 & _X012 & _X013 & _X014 & _X015 & _X016 &
_X017 & _X018 & _X019 & _X020;
_X008 = EXP(!BCD_CODE12 & REG12);
_X009 = EXP( BCD_CODE9 & !REG9);
_X010 = EXP(!BCD_CODE10 & REG10);
_X011 = EXP( BCD_CODE15 & !REG15);
_X012 = EXP(!BCD_CODE15 & REG15);
_X013 = EXP( BCD_CODE14 & !REG14);
_X014 = EXP(!BCD_CODE14 & REG14);
_X015 = EXP( BCD_CODE13 & !REG13);
_X016 = EXP(!BCD_CODE13 & REG13);
_X017 = EXP( BCD_CODE12 & !REG12);
_X018 = EXP( BCD_CODE10 & !REG10);
_X019 = EXP( BCD_CODE11 & !REG11);
_X020 = EXP(!BCD_CODE11 & REG11);
_EQ095 = !_LC030 & !_LC066 & !_LC078 & _X008 & _X009 & _X010 & _X011 &
_X012 & _X013 & _X014 & _X015 & _X016 & _X017 & _X018 &
_X019 & _X020;
_X008 = EXP(!BCD_CODE12 & REG12);
_X009 = EXP( BCD_CODE9 & !REG9);
_X010 = EXP(!BCD_CODE10 & REG10);
_X011 = EXP( BCD_CODE15 & !REG15);
_X012 = EXP(!BCD_CODE15 & REG15);
_X013 = EXP( BCD_CODE14 & !REG14);
_X014 = EXP(!BCD_CODE14 & REG14);
_X015 = EXP( BCD_CODE13 & !REG13);
_X016 = EXP(!BCD_CODE13 & REG13);
_X017 = EXP( BCD_CODE12 & !REG12);
_X018 = EXP( BCD_CODE10 & !REG10);
_X019 = EXP( BCD_CODE11 & !REG11);
_X020 = EXP(!BCD_CODE11 & REG11);
-- Node name is '~1762~2'
-- Equation name is '~1762~2', location is LC066, type is buried.
-- synthesized logic cell
_LC066 = LCELL( _EQ096 $ GND);
_EQ096 = !BCD_CODE2 & REG2
# BCD_CODE2 & !REG2
# !BCD_CODE3 & REG3
# BCD_CODE3 & !REG3
# !BCD_CODE4 & REG4;
-- Node name is '~1762~3'
-- Equation name is '~1762~3', location is LC078, type is buried.
-- synthesized logic cell
_LC078 = LCELL( _EQ097 $ GND);
_EQ097 = BCD_CODE4 & !REG4
# !BCD_CODE5 & REG5
# BCD_CODE5 & !REG5
# !BCD_CODE6 & REG6
# BCD_CODE6 & !REG6;
-- Node name is '~1762~4'
-- Equation name is '~1762~4', location is LC030, type is buried.
-- synthesized logic cell
_LC030 = LCELL( _EQ098 $ GND);
_EQ098 = !BCD_CODE7 & REG7
# BCD_CODE7 & !REG7
# !BCD_CODE8 & REG8
# BCD_CODE8 & !REG8
# !BCD_CODE9 & REG9;
-- Node name is '~1991~1'
-- Equation name is '~1991~1', location is LC068, type is buried.
-- synthesized logic cell
_LC068 = LCELL( _EQ099 $ !F0);
_EQ099 = !BCD_CODE0 & !BCD_CODE1 & !BCD_CODE2 & !BCD_CODE3 & !BCD_CODE4 &
!BCD_CODE5 & !BCD_CODE6 & BCD_CODE7 & BCD_CODE8 & !BCD_CODE9 &
BCD_CODE10 & !BCD_CODE11 & !BCD_CODE12 & BCD_CODE13 &
!BCD_CODE14 & !BCD_CODE15 & !F0
# !F0 & !QA;
-- Node name is '~1992~1'
-- Equation name is '~1992~1', location is LC003, type is buried.
-- synthesized logic cell
_LC003 = LCELL( _EQ100 $ VCC);
_EQ100 = !F2 & !_LC068 & _X021;
_X021 = EXP( F0 & !_LC086 & QA);
-- Node name is '~2001~1'
-- Equation name is '~2001~1', location is LC080, type is buried.
-- synthesized logic cell
_LC080 = LCELL( _EQ101 $ QB);
_EQ101 = !BCD_CODE0 & !BCD_CODE1 & !BCD_CODE2 & !BCD_CODE3 & !BCD_CODE4 &
!BCD_CODE5 & !BCD_CODE6 & BCD_CODE7 & BCD_CODE8 & !BCD_CODE9 &
BCD_CODE10 & !BCD_CODE11 & !BCD_CODE12 & BCD_CODE13 &
!BCD_CODE14 & !BCD_CODE15 & !F0 & !QB
# F0 & _LC086 & !QB;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs A, B, C
Project Information c:\vhdl\disk\ch8\ctrl.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:02
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 23,502K
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