📄 ctrl.rpt
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Project Information c:\vhdl\disk\ch8\ctrl.rpt
MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 06/25/2000 09:21:06
Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
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their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
CTRL
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
ctrl EPM7096LC68-7 4 27 0 78 23 81 %
User Pins: 4 27 0
Project Information c:\vhdl\disk\ch8\ctrl.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'CLK_4M' chosen for auto global Clock
Project Information c:\vhdl\disk\ch8\ctrl.rpt
** FILE HIERARCHY **
|lpm_add_sub:217|
|lpm_add_sub:217|addcore:adder|
|lpm_add_sub:217|addcore:adder|addcore:adder2|
|lpm_add_sub:217|addcore:adder|addcore:adder1|
|lpm_add_sub:217|addcore:adder|addcore:adder0|
|lpm_add_sub:217|altshift:result_ext_latency_ffs|
|lpm_add_sub:217|altshift:carry_ext_latency_ffs|
|lpm_add_sub:217|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1130|
|lpm_add_sub:1130|addcore:adder|
|lpm_add_sub:1130|addcore:adder|addcore:adder0|
|lpm_add_sub:1130|altshift:result_ext_latency_ffs|
|lpm_add_sub:1130|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1130|altshift:oflow_ext_latency_ffs|
|debouncing:U1|
|debouncing:U2|
|debouncing:U3|
Device-Specific Information: c:\vhdl\disk\ch8\ctrl.rpt
ctrl
***** Logic for device 'ctrl' compiled without errors.
Device: EPM7096LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
B B
N C C B N
U D D C U R R R R
M _ _ D M E E E E
B C C _ B V C S S S S
_ O O C _ C L E E V E E
C D D O C C K R R C R R
N E E G D N I G G G _ G V V C V V
T 1 1 N E T N N N N 4 N E E I E E
2 5 1 D 7 1 T D D D M D D D O D D
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
KEY_IN2 | 10 60 | RESERVED
VCCIO | 11 59 | RESERVED
KEY_IN1 | 12 58 | GND
BCD_CODE3 | 13 57 | RESERVED
BCD_CODE2 | 14 56 | FLAG_FUNC
BCD_CODE5 | 15 55 | RESERVED
GND | 16 54 | RESERVED
BCD_CODE6 | 17 53 | VCCIO
BCD_CODE1 | 18 EPM7096LC68-7 52 | RESERVED
BCD_CODE14 | 19 51 | RESERVED
BCD_CODE9 | 20 50 | RESERVED
VCCIO | 21 49 | RESERVED
BCD_CODE10 | 22 48 | GND
BCD_CODE13 | 23 47 | ENLOCK
KEY_IN0 | 24 46 | RESERVED
CLEAR | 25 45 | CLK_SCAN1
GND | 26 44 | RESERVED
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
F N B B V B B G V C R G R C R C V
L U C C C C C N C L E N E L E L C
A M D D C D D D C K S D S K S K C
G B _ _ I _ _ I _ E E _ E _ I
_ _ C C O C C N S R R S R S O
N C O O O O T C V V C V C
U N D D D D A E E A E A
M T E E E E N D D N D N
B 0 1 4 0 8 0 3 2
2
N.C. = No Connect, This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: c:\vhdl\disk\ch8\ctrl.rpt
ctrl
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 9/16( 56%) 8/ 8(100%) 3/16( 18%) 22/36( 61%)
B: LC17 - LC32 12/16( 75%) 8/ 8(100%) 2/16( 12%) 24/36( 66%)
C: LC33 - LC48 15/16( 93%) 8/ 8(100%) 1/16( 6%) 19/36( 52%)
D: LC49 - LC64 16/16(100%) 4/ 8( 50%) 10/16( 62%) 12/36( 33%)
E: LC65 - LC80 12/16( 75%) 1/ 8( 12%) 2/16( 12%) 32/36( 88%)
F: LC81 - LC96 14/16( 87%) 1/ 8( 12%) 14/16( 87%) 27/36( 75%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 30/48 ( 62%)
Total logic cells used: 78/96 ( 81%)
Total shareable expanders used: 23/96 ( 23%)
Total Turbo logic cells used: 78/96 ( 81%)
Total shareable expanders not available (n/a): 9/96 ( 9%)
Average fan-in: 6.41
Total fan-in: 500
Total input pins required: 4
Total output pins required: 27
Total bidirectional pins required: 0
Total logic cells required: 78
Total flipflops required: 63
Total product terms required: 255
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 21
Synthesized logic cells: 7/ 96 ( 7%)
Device-Specific Information: c:\vhdl\disk\ch8\ctrl.rpt
ctrl
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
67 - - INPUT G 0 0 0 0 0 0 0 CLK_4M
24 (48) (C) INPUT 0 0 0 0 0 0 1 KEY_IN0
12 (4) (A) INPUT 0 0 0 0 0 0 1 KEY_IN1
10 (6) (A) INPUT 0 0 0 0 0 0 1 KEY_IN2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\vhdl\disk\ch8\ctrl.rpt
ctrl
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
32 35 C FF t 1 1 0 0 8 2 4 BCD_CODE0 (:116)
18 25 B FF t 1 1 0 0 8 2 4 BCD_CODE1 (:115)
14 32 B FF t 1 1 0 0 8 2 4 BCD_CODE2 (:114)
13 1 A FF t 1 1 0 0 8 2 4 BCD_CODE3 (:113)
30 37 C FF t 1 1 0 0 9 2 5 BCD_CODE4 (:112)
15 29 B FF t 1 1 0 0 9 2 4 BCD_CODE5 (:111)
17 27 B FF t 1 1 0 0 9 2 4 BCD_CODE6 (:110)
5 14 A FF t 1 1 0 0 9 2 4 BCD_CODE7 (:109)
33 33 C FF t 1 1 0 0 9 2 4 BCD_CODE8 (:108)
20 21 B FF t 1 1 0 0 9 2 5 BCD_CODE9 (:107)
22 19 B FF t 1 1 0 0 9 2 4 BCD_CODE10 (:106)
7 12 A FF t 1 1 0 0 9 2 4 BCD_CODE11 (:105)
29 40 C FF t 1 1 0 0 9 1 4 BCD_CODE12 (:104)
23 17 B FF t 1 1 0 0 9 1 4 BCD_CODE13 (:103)
19 24 B FF t 1 1 0 0 9 1 4 BCD_CODE14 (:102)
8 9 A FF t 1 1 0 0 9 1 4 BCD_CODE15 (:101)
25 45 C OUTPUT t 0 0 0 0 2 0 0 CLEAR
36 49 D OUTPUT t 0 0 0 0 2 0 0 CLK_SCAN0
45 64 D OUTPUT t 0 0 0 0 2 0 0 CLK_SCAN1
42 59 D OUTPUT t 0 0 0 0 2 0 0 CLK_SCAN2
40 56 D OUTPUT t 0 0 0 0 2 0 0 CLK_SCAN3
47 67 E OUTPUT t 0 0 0 0 2 0 0 ENLOCK
56 81 F OUTPUT t 0 0 0 0 2 0 0 FLAG_FUNC
27 43 C OUTPUT t 0 0 0 0 4 0 0 FLAG_NUMB
28 41 C FF t 1 1 0 0 7 2 18 NUMB_CNT0 (:119)
4 16 A FF t 1 1 0 0 8 1 18 NUMB_CNT1 (:118)
9 8 A FF t 1 1 0 0 9 19 18 NUMB_CNT2 (:117)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\vhdl\disk\ch8\ctrl.rpt
ctrl
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(24) 48 C DFFE t 0 0 0 1 1 0 1 |debouncing:U1|dff1
- 47 C DFFE t 0 0 0 0 2 0 1 |debouncing:U1|dff2
- 46 C DFFE t 0 0 0 0 2 0 7 |debouncing:U1|d0 (|debouncing:U1|:13)
- 60 D DFFE t 0 0 0 0 2 0 6 |debouncing:U1|d1 (|debouncing:U1|:14)
- 39 C DFFE t 0 0 0 1 1 0 1 |debouncing:U2|dff1
- 38 C DFFE t 0 0 0 0 2 0 1 |debouncing:U2|dff2
- 36 C DFFE t 0 0 0 0 2 0 7 |debouncing:U2|d0 (|debouncing:U2|:13)
- 63 D DFFE t 0 0 0 0 2 0 6 |debouncing:U2|d1 (|debouncing:U2|:14)
- 20 B DFFE t 0 0 0 1 1 0 1 |debouncing:U3|dff1
- 44 C DFFE t 0 0 0 0 2 0 1 |debouncing:U3|dff2
- 22 B DFFE t 0 0 0 0 2 0 7 |debouncing:U3|d0 (|debouncing:U3|:13)
- 62 D DFFE t 0 0 0 0 2 0 6 |debouncing:U3|d1 (|debouncing:U3|:14)
- 50 D TFFE + t 0 0 0 0 5 4 6 Q5 (:49)
- 54 D TFFE + t 0 0 0 0 4 4 7 Q4 (:50)
- 55 D TFFE + t 0 0 0 0 3 0 2 Q3 (:51)
- 18 B TFFE + t 0 0 0 0 2 0 3 Q2 (:52)
(61) 89 F TFFE + t 0 0 0 0 1 0 4 Q1 (:53)
(57) 84 F TFFE + t 0 0 0 0 0 0 43 Q0 (:54)
(41) 57 D DFFE t 5 3 0 0 9 20 0 N3 (:87)
(44) 61 D DFFE t 4 3 1 0 9 20 0 N2 (:88)
- 58 D DFFE t 4 3 1 0 9 20 0 N1 (:89)
(37) 51 D DFFE t 4 3 1 0 9 20 0 N0 (:90)
- 52 D DFFE t 1 0 1 0 9 1 19 F2 (:92)
(39) 53 D DFFE t 1 0 1 0 9 1 4 F0 (:94)
- 85 F DFFE t 0 0 0 0 3 20 1 R0 (:95)
- 34 C DFFE t 0 0 0 0 2 20 0 R1 (:96)
- 91 F TFFE t 0 0 0 0 7 0 2 REG15 (:121)
(62) 92 F TFFE t 0 0 0 0 7 0 2 REG14 (:122)
- 82 F TFFE t 0 0 0 0 7 0 2 REG13 (:123)
- 90 F TFFE t 0 0 0 0 7 0 2 REG12 (:124)
- 95 F TFFE t 0 0 0 0 7 0 2 REG11 (:125)
(64) 94 F TFFE t 0 0 0 0 7 0 2 REG10 (:126)
- 87 F TFFE t 0 0 0 0 7 0 3 REG9 (:127)
(51) 73 E TFFE t 0 0 0 0 7 0 2 REG8 (:128)
(46) 65 E TFFE t 0 0 0 0 7 0 2 REG7 (:129)
- 74 E TFFE t 0 0 0 0 7 0 2 REG6 (:130)
(52) 75 E TFFE t 0 0 0 0 7 0 2 REG5 (:131)
- 76 E TFFE t 0 0 0 0 7 0 3 REG4 (:132)
- 79 E TFFE t 0 0 0 0 7 0 2 REG3 (:133)
(54) 77 E TFFE t 0 0 0 0 7 0 2 REG2 (:134)
- 83 F TFFE t 0 0 0 0 7 0 2 REG1 (:135)
- 93 F TFFE t 0 0 0 0 7 0 2 REG0 (:136)
- 2 A DFFE t 1 1 0 0 6 1 3 QA (:137)
- 5 A DFFE t 1 1 0 0 7 1 2 QB (:138)
(59) 86 F SOFT s t 14 0 1 0 21 0 2 ~1762~1
- 66 E SOFT s t 1 0 1 0 6 0 1 ~1762~2
- 78 E SOFT s t 1 0 1 0 6 0 1 ~1762~3
- 30 B SOFT s t 1 0 1 0 6 0 1 ~1762~4
- 68 E SOFT s t 0 0 0 0 18 0 1 ~1991~1
- 3 A SOFT s t 1 0 0 0 5 0 1 ~1992~1
(55) 80 E SOFT s t 0 0 0 0 19 0 1 ~2001~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\vhdl\disk\ch8\ctrl.rpt
ctrl
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----------------- LC1 BCD_CODE3
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