scan.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 43 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;

ENTITY scan IS
	PORT (  
			CLK      : IN STD_LOGIC ;                        --system original clock
	        Q_OUT     : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);    --count result of "clk"
			CNT_OUT  : OUT STD_LOGIC_VECTOR (1 downto 0);    --keyboard scan about 16Hz
			CLK_SCAN : OUT STD_LOGIC_VECTOR (3 downto 0)     --keyboard scan sque.
		); 
END scan ; 

ARCHITECTURE a OF scan IS
	Signal  Q    : STD_LOGIC_VECTOR(19 DOWNTO 0);           	
 	Signal 	CNT, S : STD_LOGIC_VECTOR(1 DOWNTO 0);  --keyboard scan about 15Hz ***
	SIGNAL 	SEL   : STD_LOGIC_VECTOR (3 downto 0);
Begin
	
	PROCESS (Clk)				       
	Begin
		IF CLK'Event AND CLK='1' then
			Q <= Q+1;
--			CNT <= Q(18 DOWNTO 17) ;	-- about 15Hz  61/4=15	
			CNT <= Q(4 DOWNTO 3) ;	    -- ***
		END IF;
	END PROCESS;
									     
			SEL <= 	"1110" WHEN S=0 ELSE
					"1101" WHEN S=1 ELSE
					"1011" WHEN S=2 ELSE
					"0111" WHEN S=3 ELSE
					"1111";

	S <= CNT ;        -- *** 
	CNT_OUT <= CNT ;  -- *** 
	Q_OUT <= Q ;   
	CLK_SCAN <= SEL ;
 
END a ;