sipo.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 30 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
--
--***********************************************
 ENTITY sipo IS
    PORT(
		D_IN  :IN STD_LOGIC;
		CLK   :IN STD_LOGIC;
		D_OUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END sipo;
--
--***********************************************
ARCHITECTURE a OF sipo IS
	SIGNAL Q: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
    PROCESS(CLK)
    BEGIN
		IF CLK'EVENT AND CLK = '1' THEN
	    	Q(0) <= D_IN;
			FOR I IN 1 TO 3 LOOP	
				Q(I) <= Q(I-1);
			END LOOP;
		END IF;
    END PROCESS;
	D_OUT <= Q;
END a;