free_counter.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

--*********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;

--*********************************************
ENTITY free_counter IS
	PORT  (
			CLK     :  IN   STD_LOGIC ;
			CLK_A   :  OUT  STD_LOGIC ;
			CLK_B   :  OUT  STD_LOGIC_VECTOR(1 DOWNTO 0)
		  ) ;
	END free_counter ;
			
--*********************************************
--  
ARCHITECTURE a OF free_counter IS
	SIGNAL  Q   : STD_LOGIC_VECTOR(6 DOWNTO 0);           	
BEGIN

	PROCESS (CLK)				       
	BEGIN
		IF CLK'EVENT AND CLK = '1' THEN
			Q <= Q + 1;
		END IF;
	END PROCESS;
			CLK_A <= Q(1) ;
			CLK_B <= Q(4 DOWNTO 3) ;
END a ;
--*********************************************
--