📄 display.vhd
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-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--
--*********************************************
ENTITY display is
PORT(
CLK : in STD_LOGIC; --system clock
C_DISPLAY : in STD_LOGIC_VECTOR(1 DOWNTO 0) ; --CLK for display
ACC : in STD_LOGIC_VECTOR (15 downto 0); --digit data 4 numbers
DBOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ; --showing data
SEGOUT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- SEG7 Display O/P
SELOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) -- Select SEG7 O/P
);
END display ;
--
--*********************************************
ARCHITECTURE a OF display IS
SIGNAL DB : STD_LOGIC_VECTOR( 3 DOWNTO 0); -- Number Display Signal
SIGNAL SEG : STD_LOGIC_VECTOR( 6 DOWNTO 0); -- SEG7 Display Signal
SIGNAL SEL : STD_LOGIC_VECTOR( 3 DOWNTO 0); -- Select SEG7 Signal
Signal S : STD_LOGIC_VECTOR(1 DOWNTO 0) ; -- display scan sequence
BEGIN
Connection : Block
Begin
SELOUT <= SEL ; -- Seg7 Disp Selection
SEGOUT(6 DOWNTO 0) <= SEG; -- Seven Segment Display
S <= C_DISPLAY ;
DBOUT <= DB ;
End Block Connection;
--
--**********************************************
--
--**********************************************
MULTIPLEXER : BLOCK
BEGIN
-- to decide which data will send out
DB <= ACC(15 DOWNTO 12) WHEN S = 0 ELSE
ACC(11 DOWNTO 8) WHEN S = 1 ELSE
ACC(7 DOWNTO 4) WHEN S = 2 ELSE
ACC(3 DOWNTO 0) ;
-- to decide which 7_segment can display
SEL <= "1110" WHEN S=0 ELSE
"1101" WHEN S=1 ELSE
"1011" WHEN S=2 ELSE
"0111" ;
End Block MULTIPLEXER ;
--**********************************************
--
SEVEN_SEGMENT : Block -- Binary Code -> Segment 7 Code
Begin
--gfedcba
SEG <= "0111111" WHEN DB = 0 ELSE
"0000110" WHEN DB = 1 ELSE
"1011011" WHEN DB = 2 ELSE
"1001111" WHEN DB = 3 ELSE
"1100110" WHEN DB = 4 ELSE
"1101101" WHEN DB = 5 ELSE
"1111101" WHEN DB = 6 ELSE
"0000111" WHEN DB = 7 ELSE
"1111111" WHEN DB = 8 ELSE
"1101111" WHEN DB = 9 ELSE
"0001000";
End Block SEVEN_SEGMENT;
END a;
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