📄 scan.rpt
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| | | | | | | +----------------- LC17 Q_OUT11
| | | | | | | | +--------------- LC21 Q_OUT12
| | | | | | | | | +------------- LC22 Q_OUT13
| | | | | | | | | | +----------- LC31 Q_OUT14
| | | | | | | | | | | +--------- LC26 Q_OUT15
| | | | | | | | | | | | +------- LC25 Q_OUT16
| | | | | | | | | | | | | +----- LC24 Q_OUT17
| | | | | | | | | | | | | | +--- LC23 Q_OUT18
| | | | | | | | | | | | | | | +- LC20 Q_OUT19
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC19 -> - - - - - - - - - - - - - - - * | - * | <-- |LPM_ADD_SUB:138|addcore:adder|addcore:adder0|cout_node
LC18 -> - - - - - - - - - - - - - - * - | - * | <-- |LPM_ADD_SUB:138|addcore:adder|addcore:adder1|cout_node
LC27 -> * * * * * * * * * * * * * * - - | - * | <-- Q_OUT6
LC28 -> * * - * * * * * * * * * * * - - | - * | <-- Q_OUT7
LC29 -> - * - - * * * * * * * * * * - * | - * | <-- Q_OUT8
LC30 -> - * - - - * * * * * * * * * - * | - * | <-- Q_OUT9
LC32 -> - * - - - - * * * * * * * * - * | - * | <-- Q_OUT10
LC17 -> - * - - - - - * * * * * * * - * | - * | <-- Q_OUT11
LC21 -> - * - - - - - - * * * * * * - * | - * | <-- Q_OUT12
LC22 -> - * - - - - - - - * * * * * - * | - * | <-- Q_OUT13
LC31 -> - * - - - - - - - - * * * * - * | - * | <-- Q_OUT14
LC26 -> - * - - - - - - - - - * * * - * | - * | <-- Q_OUT15
LC25 -> - - - - - - - - - - - - * * * * | - * | <-- Q_OUT16
LC24 -> - - - - - - - - - - - - - * * * | - * | <-- Q_OUT17
LC23 -> - - - - - - - - - - - - - - * * | - * | <-- Q_OUT18
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- CLK
LC4 -> * * * * * * * * * * * * * * - - | * * | <-- Q_OUT0
LC2 -> * * * * * * * * * * * * * * - - | * * | <-- Q_OUT1
LC5 -> * * * * * * * * * * * * * * - - | * * | <-- Q_OUT2
LC1 -> * * * * * * * * * * * * * * - - | * * | <-- Q_OUT3
LC3 -> * * * * * * * * * * * * * * - - | * * | <-- Q_OUT4
LC8 -> * * * * * * * * * * * * * * - - | - * | <-- Q_OUT5
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\ch8\ch8vhdl\scan.rpt
scan
** EQUATIONS **
CLK : INPUT;
-- Node name is 'CLK_SCAN0'
-- Equation name is 'CLK_SCAN0', location is LC010, type is output.
CLK_SCAN0 = LCELL( _EQ001 $ VCC);
_EQ001 = !CNT_OUT0 & !CNT_OUT1;
-- Node name is 'CLK_SCAN1'
-- Equation name is 'CLK_SCAN1', location is LC009, type is output.
CLK_SCAN1 = LCELL( _EQ002 $ VCC);
_EQ002 = CNT_OUT0 & !CNT_OUT1;
-- Node name is 'CLK_SCAN2'
-- Equation name is 'CLK_SCAN2', location is LC007, type is output.
CLK_SCAN2 = LCELL( _EQ003 $ VCC);
_EQ003 = !CNT_OUT0 & CNT_OUT1;
-- Node name is 'CLK_SCAN3'
-- Equation name is 'CLK_SCAN3', location is LC006, type is output.
CLK_SCAN3 = LCELL( _EQ004 $ VCC);
_EQ004 = CNT_OUT0 & CNT_OUT1;
-- Node name is 'CNT_OUT0' = 'CNT0'
-- Equation name is 'CNT_OUT0', location is LC012, type is output.
CNT_OUT0 = DFFE( Q_OUT3 $ GND, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'CNT_OUT1' = 'CNT1'
-- Equation name is 'CNT_OUT1', location is LC016, type is output.
CNT_OUT1 = DFFE( Q_OUT4 $ GND, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'Q_OUT0' = 'Q0'
-- Equation name is 'Q_OUT0', location is LC004, type is output.
Q_OUT0 = TFFE( VCC, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'Q_OUT1' = 'Q1'
-- Equation name is 'Q_OUT1', location is LC002, type is output.
Q_OUT1 = TFFE( Q_OUT0, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'Q_OUT2' = 'Q2'
-- Equation name is 'Q_OUT2', location is LC005, type is output.
Q_OUT2 = TFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = Q_OUT0 & Q_OUT1;
-- Node name is 'Q_OUT3' = 'Q3'
-- Equation name is 'Q_OUT3', location is LC001, type is output.
Q_OUT3 = TFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = Q_OUT0 & Q_OUT1 & Q_OUT2;
-- Node name is 'Q_OUT4' = 'Q4'
-- Equation name is 'Q_OUT4', location is LC003, type is output.
Q_OUT4 = TFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3;
-- Node name is 'Q_OUT5' = 'Q5'
-- Equation name is 'Q_OUT5', location is LC008, type is output.
Q_OUT5 = TFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3 & Q_OUT4;
-- Node name is 'Q_OUT6' = 'Q6'
-- Equation name is 'Q_OUT6', location is LC027, type is output.
Q_OUT6 = TFFE( _EQ009, GLOBAL( CLK), VCC, VCC, VCC);
_EQ009 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3 & Q_OUT4 & Q_OUT5;
-- Node name is 'Q_OUT7' = 'Q7'
-- Equation name is 'Q_OUT7', location is LC028, type is output.
Q_OUT7 = TFFE( _EQ010, GLOBAL( CLK), VCC, VCC, VCC);
_EQ010 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3 & Q_OUT4 & Q_OUT5 &
Q_OUT6;
-- Node name is 'Q_OUT8' = 'Q8'
-- Equation name is 'Q_OUT8', location is LC029, type is output.
Q_OUT8 = TFFE( _EQ011, GLOBAL( CLK), VCC, VCC, VCC);
_EQ011 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3 & Q_OUT4 & Q_OUT5 &
Q_OUT6 & Q_OUT7;
-- Node name is 'Q_OUT9' = 'Q9'
-- Equation name is 'Q_OUT9', location is LC030, type is output.
Q_OUT9 = TFFE( _EQ012, GLOBAL( CLK), VCC, VCC, VCC);
_EQ012 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3 & Q_OUT4 & Q_OUT5 &
Q_OUT6 & Q_OUT7 & Q_OUT8;
-- Node name is 'Q_OUT10' = 'Q10'
-- Equation name is 'Q_OUT10', location is LC032, type is output.
Q_OUT10 = TFFE( _EQ013, GLOBAL( CLK), VCC, VCC, VCC);
_EQ013 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3 & Q_OUT4 & Q_OUT5 &
Q_OUT6 & Q_OUT7 & Q_OUT8 & Q_OUT9;
-- Node name is 'Q_OUT11' = 'Q11'
-- Equation name is 'Q_OUT11', location is LC017, type is output.
Q_OUT11 = TFFE( _EQ014, GLOBAL( CLK), VCC, VCC, VCC);
_EQ014 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3 & Q_OUT4 & Q_OUT5 &
Q_OUT6 & Q_OUT7 & Q_OUT8 & Q_OUT9 & Q_OUT10;
-- Node name is 'Q_OUT12' = 'Q12'
-- Equation name is 'Q_OUT12', location is LC021, type is output.
Q_OUT12 = TFFE( _EQ015, GLOBAL( CLK), VCC, VCC, VCC);
_EQ015 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3 & Q_OUT4 & Q_OUT5 &
Q_OUT6 & Q_OUT7 & Q_OUT8 & Q_OUT9 & Q_OUT10 & Q_OUT11;
-- Node name is 'Q_OUT13' = 'Q13'
-- Equation name is 'Q_OUT13', location is LC022, type is output.
Q_OUT13 = TFFE( _EQ016, GLOBAL( CLK), VCC, VCC, VCC);
_EQ016 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3 & Q_OUT4 & Q_OUT5 &
Q_OUT6 & Q_OUT7 & Q_OUT8 & Q_OUT9 & Q_OUT10 & Q_OUT11 &
Q_OUT12;
-- Node name is 'Q_OUT14' = 'Q14'
-- Equation name is 'Q_OUT14', location is LC031, type is output.
Q_OUT14 = TFFE( _EQ017, GLOBAL( CLK), VCC, VCC, VCC);
_EQ017 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3 & Q_OUT4 & Q_OUT5 &
Q_OUT6 & Q_OUT7 & Q_OUT8 & Q_OUT9 & Q_OUT10 & Q_OUT11 &
Q_OUT12 & Q_OUT13;
-- Node name is 'Q_OUT15' = 'Q15'
-- Equation name is 'Q_OUT15', location is LC026, type is output.
Q_OUT15 = TFFE( _EQ018, GLOBAL( CLK), VCC, VCC, VCC);
_EQ018 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3 & Q_OUT4 & Q_OUT5 &
Q_OUT6 & Q_OUT7 & Q_OUT8 & Q_OUT9 & Q_OUT10 & Q_OUT11 &
Q_OUT12 & Q_OUT13 & Q_OUT14;
-- Node name is 'Q_OUT16' = 'Q16'
-- Equation name is 'Q_OUT16', location is LC025, type is output.
Q_OUT16 = TFFE( _EQ019, GLOBAL( CLK), VCC, VCC, VCC);
_EQ019 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3 & Q_OUT4 & Q_OUT5 &
Q_OUT6 & Q_OUT7 & Q_OUT8 & Q_OUT9 & Q_OUT10 & Q_OUT11 &
Q_OUT12 & Q_OUT13 & Q_OUT14 & Q_OUT15;
-- Node name is 'Q_OUT17' = 'Q17'
-- Equation name is 'Q_OUT17', location is LC024, type is output.
Q_OUT17 = TFFE( _EQ020, GLOBAL( CLK), VCC, VCC, VCC);
_EQ020 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3 & Q_OUT4 & Q_OUT5 &
Q_OUT6 & Q_OUT7 & Q_OUT8 & Q_OUT9 & Q_OUT10 & Q_OUT11 &
Q_OUT12 & Q_OUT13 & Q_OUT14 & Q_OUT15 & Q_OUT16;
-- Node name is 'Q_OUT18' = 'Q18'
-- Equation name is 'Q_OUT18', location is LC023, type is output.
Q_OUT18 = TFFE( _EQ021, GLOBAL( CLK), VCC, VCC, VCC);
_EQ021 = _LC018 & Q_OUT16 & Q_OUT17;
-- Node name is 'Q_OUT19' = 'Q19'
-- Equation name is 'Q_OUT19', location is LC020, type is output.
Q_OUT19 = TFFE( _EQ022, GLOBAL( CLK), VCC, VCC, VCC);
_EQ022 = _LC019 & Q_OUT8 & Q_OUT9 & Q_OUT10 & Q_OUT11 & Q_OUT12 &
Q_OUT13 & Q_OUT14 & Q_OUT15 & Q_OUT16 & Q_OUT17 & Q_OUT18;
-- Node name is '|LPM_ADD_SUB:138|addcore:adder|addcore:adder0|cout_node' from file "addcore.tdf" line 165, column 5
-- Equation name is '_LC019', type is buried
_LC019 = LCELL( _EQ023 $ GND);
_EQ023 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3 & Q_OUT4 & Q_OUT5 &
Q_OUT6 & Q_OUT7;
-- Node name is '|LPM_ADD_SUB:138|addcore:adder|addcore:adder1|cout_node' from file "addcore.tdf" line 165, column 5
-- Equation name is '_LC018', type is buried
_LC018 = LCELL( _EQ024 $ GND);
_EQ024 = Q_OUT0 & Q_OUT1 & Q_OUT2 & Q_OUT3 & Q_OUT4 & Q_OUT5 &
Q_OUT6 & Q_OUT7 & Q_OUT8 & Q_OUT9 & Q_OUT10 & Q_OUT11 &
Q_OUT12 & Q_OUT13 & Q_OUT14 & Q_OUT15;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information f:\ch8\ch8vhdl\scan.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:03
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,401K
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