📄 scan.rpt
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Project Information f:\ch8\ch8vhdl\scan.rpt
MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 06/19/2000 02:53:20
Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
SCAN
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
scan EPM7032LC44-6 1 26 0 28 0 87 %
User Pins: 1 26 0
Project Information f:\ch8\ch8vhdl\scan.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'CLK' chosen for auto global Clock
Project Information f:\ch8\ch8vhdl\scan.rpt
** FILE HIERARCHY **
|lpm_add_sub:138|
|lpm_add_sub:138|addcore:adder|
|lpm_add_sub:138|addcore:adder|addcore:adder2|
|lpm_add_sub:138|addcore:adder|addcore:adder1|
|lpm_add_sub:138|addcore:adder|addcore:adder0|
|lpm_add_sub:138|altshift:result_ext_latency_ffs|
|lpm_add_sub:138|altshift:carry_ext_latency_ffs|
|lpm_add_sub:138|altshift:oflow_ext_latency_ffs|
Device-Specific Information: f:\ch8\ch8vhdl\scan.rpt
scan
***** Logic for device 'scan' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
R
Q E
Q Q Q _ S
_ _ _ O E
O O O U R
U U U V G G G C G T V
T T T C N N N L N 1 E
4 1 3 C D D D K D 1 D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
Q_OUT0 | 7 39 | RESERVED
Q_OUT2 | 8 38 | Q_OUT19
CLK_SCAN3 | 9 37 | Q_OUT12
GND | 10 36 | Q_OUT13
CLK_SCAN2 | 11 35 | VCC
Q_OUT5 | 12 EPM7032LC44-6 34 | Q_OUT18
CLK_SCAN1 | 13 33 | Q_OUT17
CLK_SCAN0 | 14 32 | Q_OUT16
VCC | 15 31 | Q_OUT15
RESERVED | 16 30 | GND
CNT_OUT0 | 17 29 | Q_OUT6
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R C G V Q Q Q Q Q
E E E N N C _ _ _ _ _
S S S T D C O O O O O
E E E _ U U U U U
R R R O T T T T T
V V V U 1 1 9 8 7
E E E T 0 4
D D D 1
N.C. = No Connect, This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: f:\ch8\ch8vhdl\scan.rpt
scan
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 12/16( 75%) 12/16( 75%) 0/16( 0%) 7/36( 19%)
B: LC17 - LC32 16/16(100%) 14/16( 87%) 0/16( 0%) 21/36( 58%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 26/32 ( 81%)
Total logic cells used: 28/32 ( 87%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 28/32 ( 87%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 8.71
Total fan-in: 244
Total input pins required: 1
Total output pins required: 26
Total bidirectional pins required: 0
Total logic cells required: 28
Total flipflops required: 22
Total product terms required: 28
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: f:\ch8\ch8vhdl\scan.rpt
scan
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT G 0 0 0 0 0 0 0 CLK
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\ch8\ch8vhdl\scan.rpt
scan
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
14 10 A OUTPUT t 0 0 0 0 2 0 0 CLK_SCAN0
13 9 A OUTPUT t 0 0 0 0 2 0 0 CLK_SCAN1
11 7 A OUTPUT t 0 0 0 0 2 0 0 CLK_SCAN2
9 6 A OUTPUT t 0 0 0 0 2 0 0 CLK_SCAN3
17 12 A FF + t 0 0 0 0 1 4 0 CNT_OUT0 (:49)
21 16 A FF + t 0 0 0 0 1 4 0 CNT_OUT1 (:48)
7 4 A FF + t 0 0 0 0 0 17 2 Q_OUT0 (:47)
5 2 A FF + t 0 0 0 0 1 16 2 Q_OUT1 (:46)
8 5 A FF + t 0 0 0 0 2 15 2 Q_OUT2 (:45)
4 1 A FF + t 0 0 0 0 3 15 2 Q_OUT3 (:44)
6 3 A FF + t 0 0 0 0 4 14 2 Q_OUT4 (:43)
12 8 A FF + t 0 0 0 0 5 12 2 Q_OUT5 (:42)
29 27 B FF + t 0 0 0 0 6 11 2 Q_OUT6 (:41)
28 28 B FF + t 0 0 0 0 7 10 2 Q_OUT7 (:40)
27 29 B FF + t 0 0 0 0 8 10 1 Q_OUT8 (:39)
26 30 B FF + t 0 0 0 0 9 9 1 Q_OUT9 (:38)
24 32 B FF + t 0 0 0 0 10 8 1 Q_OUT10 (:37)
41 17 B FF + t 0 0 0 0 11 7 1 Q_OUT11 (:36)
37 21 B FF + t 0 0 0 0 12 6 1 Q_OUT12 (:35)
36 22 B FF + t 0 0 0 0 13 5 1 Q_OUT13 (:34)
25 31 B FF + t 0 0 0 0 14 4 1 Q_OUT14 (:33)
31 26 B FF + t 0 0 0 0 15 3 1 Q_OUT15 (:32)
32 25 B FF + t 0 0 0 0 16 3 0 Q_OUT16 (:31)
33 24 B FF + t 0 0 0 0 17 2 0 Q_OUT17 (:30)
34 23 B FF + t 0 0 0 0 3 1 0 Q_OUT18 (:29)
38 20 B FF + t 0 0 0 0 12 0 0 Q_OUT19 (:28)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\ch8\ch8vhdl\scan.rpt
scan
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(39) 19 B SOFT t 0 0 0 0 8 1 0 |LPM_ADD_SUB:138|addcore:adder|addcore:adder0|cout_node
(40) 18 B SOFT t 0 0 0 0 16 1 0 |LPM_ADD_SUB:138|addcore:adder|addcore:adder1|cout_node
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\ch8\ch8vhdl\scan.rpt
scan
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----------------------- LC10 CLK_SCAN0
| +--------------------- LC9 CLK_SCAN1
| | +------------------- LC7 CLK_SCAN2
| | | +----------------- LC6 CLK_SCAN3
| | | | +--------------- LC12 CNT_OUT0
| | | | | +------------- LC16 CNT_OUT1
| | | | | | +----------- LC4 Q_OUT0
| | | | | | | +--------- LC2 Q_OUT1
| | | | | | | | +------- LC5 Q_OUT2
| | | | | | | | | +----- LC1 Q_OUT3
| | | | | | | | | | +--- LC3 Q_OUT4
| | | | | | | | | | | +- LC8 Q_OUT5
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC12 -> * * * * - - - - - - - - | * - | <-- CNT_OUT0
LC16 -> * * * * - - - - - - - - | * - | <-- CNT_OUT1
LC4 -> - - - - - - * * * * * * | * * | <-- Q_OUT0
LC2 -> - - - - - - - * * * * * | * * | <-- Q_OUT1
LC5 -> - - - - - - - - * * * * | * * | <-- Q_OUT2
LC1 -> - - - - * - - - - * * * | * * | <-- Q_OUT3
LC3 -> - - - - - * - - - - * * | * * | <-- Q_OUT4
Pin
43 -> - - - - - - - - - - - - | - - | <-- CLK
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\ch8\ch8vhdl\scan.rpt
scan
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC19 |LPM_ADD_SUB:138|addcore:adder|addcore:adder0|cout_node
| +----------------------------- LC18 |LPM_ADD_SUB:138|addcore:adder|addcore:adder1|cout_node
| | +--------------------------- LC27 Q_OUT6
| | | +------------------------- LC28 Q_OUT7
| | | | +----------------------- LC29 Q_OUT8
| | | | | +--------------------- LC30 Q_OUT9
| | | | | | +------------------- LC32 Q_OUT10
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