siso.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 25 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY siso IS
    PORT(
		DATA_IN  :IN STD_LOGIC;
		CLK   :IN STD_LOGIC;
		DATA_OUT :OUT STD_LOGIC);
END siso ;

ARCHITECTURE a OF siso IS
	SIGNAL Q: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
    PROCESS(CLK)
    BEGIN
		IF CLK'EVENT AND CLK = '1' THEN
	    	Q(0) <= DATA_IN;
			FOR I IN 1 TO 3 LOOP	
				Q(I) <= Q(I-1);
			END LOOP;
		END IF;
    END PROCESS;
	DATA_OUT <= Q(3);
END a;