piso.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 37 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY piso IS
    PORT(
		DATA_IN  :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		CLK   :IN STD_LOGIC;
		nLOAD :IN STD_LOGIC;
		DATA_OUT :OUT STD_LOGIC);
END piso;

ARCHITECTURE a OF piso IS
	SIGNAL Q: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
    PROCESS(nLOAD,CLK)
    BEGIN
		IF nLOAD = '0' THEN
			Q <= DATA_IN;
		ELSIF  CLK'EVENT AND CLK = '1' THEN
			q(1) <= Q(0) ;
			FOR I IN 1 TO 3 LOOP
	    		Q(I) <= Q(I-1);
			END LOOP;
		END IF;
    END PROCESS;

	PROCESS(nLOAD,CLK)
	BEGIN
		IF nLOAD = '0' THEN
			DATA_OUT <= '0';
		ELSIF CLK'EVENT AND CLK = '1' THEN
			DATA_OUT <= Q(3);
		END IF;
	END PROCESS;
END a;