ch6_3_3.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 38 行

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch6_3_3 is
	PORT(
		 CP		: IN	STD_LOGIC;
		 OP		: OUT	STD_LOGIC 
		);
END Ch6_3_3;

--*********************************************
ARCHITECTURE a OF Ch6_3_3 IS
	SIGNAL  DLY 	:   STD_LOGIC;
	SIGNAL 	QN		: 	STD_LOGIC_VECTOR(3 DOWNTO 0);	   
BEGIN
											
		PROCESS (CP)				-- *** COUNTER
		BEGIN
				IF CP'event AND CP='1' THEN
					DLY <= QN(3);
					QN <= QN + 6;		-- COUNTER + 6 
				END IF;
		END PROCESS;			

		OP <= (QN(3) XOR DLY) AND NOT CP;			-- Output			
END a;