ch6_2_1.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch6_2_1 is
	PORT(
		 A,CP		: IN	STD_LOGIC;
		 Q1,Q2,Q3	: OUT	STD_LOGIC
		);
END Ch6_2_1;

--*********************************************
ARCHITECTURE a OF Ch6_2_1 IS
	SIGNAL QN1,QN2,QN3	: 	STD_LOGIC;
BEGIN
											-- *** Time Delay
		PROCESS (CP)
		BEGIN
				IF CP'event AND CP='1' THEN
 					QN3	<= QN2;					-- 3rd Stage D Flip/Flop
					QN2 <= QN1;					-- 2nd State D Flip/Flop
					QN1 <= A;					-- 1st State D Flip/Flop
				END IF;
		END PROCESS;						-- *** Time Delay

		Q3 <= QN3;							-- ** Output
		Q2 <= QN2;
		Q1 <= QN1;							-- ** Output
END a;