ch6_2_2.rpt

《VHDL与数字电路设计》配套光盘,可以实际调用

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:      d:\lu\vhdl-digitallogic\disk\ch6\ch6_2_2.rpt
ch6_2_2a

** BURIED LOGIC **

                                               Fan-In    Fan-Out
 IOC     LC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      5    B    01        DFF   +          1    0    0    4  Q1 (:6)
   -      4    B    01        DFF   +          0    1    0    3  Q2 (:7)
   -      1    B    01       AND2              0    2    1    0  :18
   -      2    B    01       AND2              0    2    1    0  :21
   -      3    B    01        OR2              0    2    1    0  :22


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:      d:\lu\vhdl-digitallogic\disk\ch6\ch6_2_2.rpt
ch6_2_2a

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

         FastTrack                                 
Row     Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/168(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)
B:       3/168(  1%)    0/16(  0%)      3/16( 18%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/16(  0%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
12:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:      d:\lu\vhdl-digitallogic\disk\ch6\ch6_2_2.rpt
ch6_2_2a

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT        2         CP


Device-Specific Information:      d:\lu\vhdl-digitallogic\disk\ch6\ch6_2_2.rpt
ch6_2_2a

** EQUATIONS **

A        : INPUT;
CP       : INPUT;

-- Node name is 'DL_OP' 
-- Equation name is 'DL_OP', type is output 
DL_OP    =  _LC3_B1;

-- Node name is 'DN_OP' 
-- Equation name is 'DN_OP', type is output 
DN_OP    =  _LC2_B1;

-- Node name is ':6' = 'Q1' 
-- Equation name is 'Q1', location is LC5_B1, type is buried.
Q1       = DFF( A, GLOBAL( CP),  VCC,  VCC);

-- Node name is ':7' = 'Q2' 
-- Equation name is 'Q2', location is LC4_B1, type is buried.
Q2       = DFF( Q1, GLOBAL( CP),  VCC,  VCC);

-- Node name is 'UP_OP' 
-- Equation name is 'UP_OP', type is output 
UP_OP    =  _LC1_B1;

-- Node name is ':18' 
-- Equation name is '_LC1_B1', type is buried 
_LC1_B1  = LCELL( _EQ001);
  _EQ001 =  Q1 & !Q2;

-- Node name is ':21' 
-- Equation name is '_LC2_B1', type is buried 
_LC2_B1  = LCELL( _EQ002);
  _EQ002 = !Q1 &  Q2;

-- Node name is ':22' 
-- Equation name is '_LC3_B1', type is buried 
_LC3_B1  = LCELL( _EQ003);
  _EQ003 = !Q1 &  Q2
         #  Q1 & !Q2;



Project Information               d:\lu\vhdl-digitallogic\disk\ch6\ch6_2_2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX8000' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,749K