ch6_1_2a.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 36 行

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch6_1_2A is
	PORT(
		 CP			: IN	STD_LOGIC;
		 Q			: OUT	STD_LOGIC
		);
END Ch6_1_2A;

--*********************************************
ARCHITECTURE a OF Ch6_1_2A IS
	SIGNAL  QN	: 	STD_LOGIC;
BEGIN
		PROCESS (CP)
		BEGIN
				IF CP'event AND CP='1' THEN
 					QN <= NOT QN;
				END IF;
		END PROCESS;

		Q <= QN;
		
END a;