ch6_3_2.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch6_3_2 is
	PORT(
		 CP		: IN	STD_LOGIC;
		 Result	: OUT	STD_LOGIC
		);
END Ch6_3_2;

--*********************************************
ARCHITECTURE a OF Ch6_3_2 IS
	SIGNAL  SET 	:   STD_LOGIC;
	SIGNAL 	QN		: 	STD_LOGIC_VECTOR(3 DOWNTO 0);	   
BEGIN
											
		PROCESS (CP)				-- *** COUNTER
		BEGIN
				IF SET = '1' THEN
					QN <= "0101";		-- Set Counter	
				ELSIF CP'event AND CP='1' THEN
					QN <= QN - 1;		-- COUNTER - 1 
				END IF;
		END PROCESS;			

		SET <= QN(3);
		Result <= QN(2);				-- Result Output			

END a;