ch6_4_1.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 52 行

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch6_4_1 is
	PORT(
		 CP			: IN	STD_LOGIC;			-- Clock
		 DIN		: IN	STD_LOGIC;			-- I/P Signal
		 DIR		: IN	STD_LOGIC;			-- Shift Control
		 OP			: OUT	STD_LOGIC 			-- Shift Result
		);
END Ch6_4_1;

--*********************************************
ARCHITECTURE a OF Ch6_4_1 IS
	SIGNAL 	Q		: 	STD_LOGIC_VECTOR(7 DOWNTO 0);	--Shift Register   
BEGIN
											
		PROCESS (CP)				
		BEGIN
				IF CP'event AND CP='1' THEN
					IF DIR = '0' THEN 		 -- Shift Left
						Q(0) <= DIN;
					
						FOR I IN 1 TO 7 LOOP
							Q(I) <= Q(I-1);
						END LOOP;
					ELSE					-- Shift Right
						Q(7) <= DIN;
					
						FOR I IN 7 DOWNTO 1 LOOP
							Q(I-1) <= Q(I);
						END LOOP;
					END IF;
					 
				END IF;
		END PROCESS;			
										-- Output
		OP <= Q(7) WHEN DIR = '0' ELSE
			  Q(0);						
END a;