ch6_2_2.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch6_2_2 is
	PORT(
		 A,CP					: IN	STD_LOGIC;
		 UP_OP,DN_OP,DL_OP		: OUT	STD_LOGIC
		);
END Ch6_2_2;

--*********************************************
ARCHITECTURE a OF Ch6_2_2 IS
	SIGNAL Q1,Q2	: 	STD_LOGIC;
BEGIN
											-- *** Time Delay
		PROCESS (CP)
		BEGIN
				IF CP'event AND CP='1' THEN
					Q2 <= Q1;				-- 2rd Stage
					Q1 <= A;				-- 1st Stage D Flip/Flop
				END IF;
		END PROCESS;						-- *** Time Delay

		UP_OP <= Q1 AND NOT Q2;				-- ** Differential 
		DN_OP <= NOT Q1 AND Q2;
		DL_OP <= Q1 XOR Q2;					-- ** Differential
END a;