ch6_3_1.vhd

来自「《VHDL与数字电路设计》配套光盘,可以实际调用」· VHDL 代码 · 共 43 行

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch6_3_1 is
	PORT(
		 CP		: IN	STD_LOGIC;
		 Result	: OUT	STD_LOGIC
		);
END Ch6_3_1;

--*********************************************
ARCHITECTURE a OF Ch6_3_1 IS
	SIGNAL  RST 	:   STD_LOGIC;
	SIGNAL 	QN		: 	STD_LOGIC_VECTOR(2 DOWNTO 0);   
BEGIN
											
		PROCESS (CP,RST)				-- *** COUNTER
		BEGIN
				IF RST = '1' THEN
					QN <= "0000";		--Reset Counter	
				ELSIF CP'event AND CP='1' THEN
					QN <= QN + 1;		--COUNTER + 1 
				END IF;
		END PROCESS;			

		RST <= 	'1' WHEN QN = 6 ELSE 		-- RESET COUNTER
				'0';		
		
		Result <= QN(2);					-- Result Output			

END a;