ch6_3_1.rpt

《VHDL与数字电路设计》配套光盘,可以实际调用

 Pin     LC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  56      -    B    --     OUTPUT              0    1    0    0  Result


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:      d:\lu\vhdl-digitallogic\disk\ch6\ch6_3_1.rpt
ch6_3_1a

** BURIED LOGIC **

                                               Fan-In    Fan-Out
 IOC     LC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      1    B    01        DFF   +          0    3    1    1  QN2 (:4)
   -      2    B    01        DFF   +          0    2    0    2  QN1 (:5)
   -      3    B    01        DFF   +          0    1    0    3  QN0 (:6)
   -      4    B    01        OR2        !     0    3    0    3  :27


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:      d:\lu\vhdl-digitallogic\disk\ch6\ch6_3_1.rpt
ch6_3_1a

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

         FastTrack                                 
Row     Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/168(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)
B:       1/168(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/16(  0%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
12:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:      d:\lu\vhdl-digitallogic\disk\ch6\ch6_3_1.rpt
ch6_3_1a

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT        3         CP


Device-Specific Information:      d:\lu\vhdl-digitallogic\disk\ch6\ch6_3_1.rpt
ch6_3_1a

** CLEAR SIGNALS **

Type     Fan-out       Name
LCELL        3         :27


Device-Specific Information:      d:\lu\vhdl-digitallogic\disk\ch6\ch6_3_1.rpt
ch6_3_1a

** EQUATIONS **

CP       : INPUT;

-- Node name is ':6' = 'QN0' 
-- Equation name is 'QN0', location is LC3_B1, type is buried.
QN0      = DFF(!QN0, GLOBAL( CP), !_LC4_B1,  VCC);

-- Node name is ':5' = 'QN1' 
-- Equation name is 'QN1', location is LC2_B1, type is buried.
QN1      = DFF( _EQ001, GLOBAL( CP), !_LC4_B1,  VCC);
  _EQ001 =  QN0 & !QN1
         # !QN0 &  QN1;

-- Node name is ':4' = 'QN2' 
-- Equation name is 'QN2', location is LC1_B1, type is buried.
QN2      = DFF( _EQ002, GLOBAL( CP), !_LC4_B1,  VCC);
  _EQ002 = !QN0 &  QN2
         # !QN1 &  QN2
         #  QN0 &  QN1 & !QN2;

-- Node name is 'Result' 
-- Equation name is 'Result', type is output 
Result   =  QN2;

-- Node name is ':27' 
-- Equation name is '_LC4_B1', type is buried 
!_LC4_B1 = _LC4_B1~NOT;
_LC4_B1~NOT = LCELL( _EQ003);
  _EQ003 =  QN0
         # !QN2
         # !QN1;



Project Information               d:\lu\vhdl-digitallogic\disk\ch6\ch6_3_1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX8000' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 6,168K