ch6_2_3a.rpt

《VHDL与数字电路设计》配套光盘,可以实际调用

  56      -    B    --     OUTPUT              0    1    0    0  Q2
  58      -    B    --     OUTPUT              0    1    0    0  Q3


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:     d:\lu\vhdl-digitallogic\disk\ch6\ch6_2_3a.rpt
ch6_2_3a

** BURIED LOGIC **

                                               Fan-In    Fan-Out
 IOC     LC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      4    B    01        DFF   +          0    3    1    0  QN3 (:6)
   -      1    B    01        DFF   +          0    2    1    1  QN2 (:7)
   -      2    B    01        DFF   +          0    1    1    2  QN1 (:8)
   -      3    B    01        DFF   +          0    0    1    3  QN0 (:9)


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:     d:\lu\vhdl-digitallogic\disk\ch6\ch6_2_3a.rpt
ch6_2_3a

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

         FastTrack                                 
Row     Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/168(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)
B:       4/168(  2%)    0/16(  0%)      4/16( 25%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/16(  0%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
12:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:     d:\lu\vhdl-digitallogic\disk\ch6\ch6_2_3a.rpt
ch6_2_3a

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT        4         CP


Device-Specific Information:     d:\lu\vhdl-digitallogic\disk\ch6\ch6_2_3a.rpt
ch6_2_3a

** EQUATIONS **

CP       : INPUT;

-- Node name is ':9' = 'QN0' 
-- Equation name is 'QN0', location is LC3_B1, type is buried.
QN0      = DFF(!QN0, GLOBAL( CP),  VCC,  VCC);

-- Node name is ':8' = 'QN1' 
-- Equation name is 'QN1', location is LC2_B1, type is buried.
QN1      = DFF( _EQ001, GLOBAL( CP),  VCC,  VCC);
  _EQ001 = !QN0 &  QN1
         #  QN0 & !QN1;

-- Node name is ':7' = 'QN2' 
-- Equation name is 'QN2', location is LC1_B1, type is buried.
QN2      = DFF( _EQ002, GLOBAL( CP),  VCC,  VCC);
  _EQ002 = !QN1 &  QN2
         # !QN0 &  QN2
         #  QN0 &  QN1 & !QN2;

-- Node name is ':6' = 'QN3' 
-- Equation name is 'QN3', location is LC4_B1, type is buried.
QN3      = DFF( _EQ003, GLOBAL( CP),  VCC,  VCC);
  _EQ003 = !QN1 &  QN3
         # !QN0 &  QN3
         # !QN2 &  QN3
         #  QN0 &  QN1 &  QN2 & !QN3;

-- Node name is 'Q0' 
-- Equation name is 'Q0', type is output 
Q0       =  QN0;

-- Node name is 'Q1' 
-- Equation name is 'Q1', type is output 
Q1       =  QN1;

-- Node name is 'Q2' 
-- Equation name is 'Q2', type is output 
Q2       =  QN2;

-- Node name is 'Q3' 
-- Equation name is 'Q3', type is output 
Q3       =  QN3;



Project Information              d:\lu\vhdl-digitallogic\disk\ch6\ch6_2_3a.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX8000' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 6,207K