ch6_1_3.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch6_1_3 is
	PORT(
		 S,R		: IN	STD_LOGIC;
		 Q,NOT_Q	: OUT	STD_LOGIC
		);
END Ch6_1_3;

--*********************************************
ARCHITECTURE a OF Ch6_1_3 IS
	SIGNAL  QN,NOT_QN		: 	STD_LOGIC;
BEGIN
		
		QN 	  	<= R NOR NOT_QN;
		NOT_QN 	<= S NOR QN; 

		Q 	  <= QN;
		NOT_Q <= NOT_QN;
		
END a;