ch6_1_2b.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch6_1_2B is
	PORT(
		 CLK		: IN	STD_LOGIC;
		 Q0,Q1,Q2	: OUT	STD_LOGIC
		);
END Ch6_1_2B;

--*********************************************
ARCHITECTURE a OF Ch6_1_2B IS
	SIGNAL  QN0,QN1,QN2		: 	STD_LOGIC;
BEGIN
		PROCESS (CLK,QN0,QN1)
		BEGIN
				IF CLK'event AND CLK='1' THEN
 					QN0 <= NOT QN0;
				END IF;

				IF QN0'event AND QN0='1' THEN
 					QN1 <= NOT QN1;
				END IF;

				IF QN1'event AND QN1='1' THEN
 					QN2 <= NOT QN2;
				END IF;

		END PROCESS;

		Q0 <= QN0;
		Q1 <= QN1;
		Q2 <= QN2;
		
END a;