ch6_1_1.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch6_1_1 is
	PORT(
		 CP,D		: IN	STD_LOGIC;
		 Q			: OUT	STD_LOGIC
		);
END Ch6_1_1;

--*********************************************
ARCHITECTURE a OF Ch6_1_1 IS
BEGIN
		PROCESS (CP)
		BEGIN
				IF CP'event AND CP='1' THEN
 					Q <= D;
				END IF;
		END PROCESS;
		
END a;