📄 ch6_4_1.rpt
字号:
IOC LC Row Col Primitive Code INP FBK OUT FBK Name
- 1 B 02 DFF + 2 1 0 2 Q7 (:5)
- 7 B 02 DFF + 1 2 0 2 Q6 (:6)
- 6 B 02 DFF + 1 2 0 2 Q5 (:7)
- 8 B 02 DFF + 1 2 0 2 Q4 (:8)
- 5 B 02 DFF + 1 2 0 2 Q3 (:9)
- 3 B 02 DFF + 1 2 0 2 Q2 (:10)
- 4 B 02 DFF + 1 2 0 2 Q1 (:11)
- 2 B 02 DFF + 2 1 0 2 Q0 (:12)
- 1 B 01 OR2 1 2 1 0 :1142
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch6\ch6_4_1.rpt
ch6_4_1a
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
FastTrack
Row Interconnect Input Pins Output Pins Bidir Pins
A: 0/168( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 3/168( 1%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/16( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/16( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch6\ch6_4_1.rpt
ch6_4_1a
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CP
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch6\ch6_4_1.rpt
ch6_4_1a
** EQUATIONS **
CP : INPUT;
DIN : INPUT;
DIR : INPUT;
-- Node name is 'OP'
-- Equation name is 'OP', type is output
OP = _LC1_B1;
-- Node name is ':12' = 'Q0'
-- Equation name is 'Q0', location is LC2_B2, type is buried.
Q0 = DFF( _EQ001, GLOBAL( CP), VCC, VCC);
_EQ001 = DIR & Q1
# DIN & !DIR;
-- Node name is ':11' = 'Q1'
-- Equation name is 'Q1', location is LC4_B2, type is buried.
Q1 = DFF( _EQ002, GLOBAL( CP), VCC, VCC);
_EQ002 = !DIR & Q0
# DIR & Q2;
-- Node name is ':10' = 'Q2'
-- Equation name is 'Q2', location is LC3_B2, type is buried.
Q2 = DFF( _EQ003, GLOBAL( CP), VCC, VCC);
_EQ003 = !DIR & Q1
# DIR & Q3;
-- Node name is ':9' = 'Q3'
-- Equation name is 'Q3', location is LC5_B2, type is buried.
Q3 = DFF( _EQ004, GLOBAL( CP), VCC, VCC);
_EQ004 = !DIR & Q2
# DIR & Q4;
-- Node name is ':8' = 'Q4'
-- Equation name is 'Q4', location is LC8_B2, type is buried.
Q4 = DFF( _EQ005, GLOBAL( CP), VCC, VCC);
_EQ005 = !DIR & Q3
# DIR & Q5;
-- Node name is ':7' = 'Q5'
-- Equation name is 'Q5', location is LC6_B2, type is buried.
Q5 = DFF( _EQ006, GLOBAL( CP), VCC, VCC);
_EQ006 = !DIR & Q4
# DIR & Q6;
-- Node name is ':6' = 'Q6'
-- Equation name is 'Q6', location is LC7_B2, type is buried.
Q6 = DFF( _EQ007, GLOBAL( CP), VCC, VCC);
_EQ007 = !DIR & Q5
# DIR & Q7;
-- Node name is ':5' = 'Q7'
-- Equation name is 'Q7', location is LC1_B2, type is buried.
Q7 = DFF( _EQ008, GLOBAL( CP), VCC, VCC);
_EQ008 = !DIR & Q6
# DIN & DIR;
-- Node name is ':1142'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = LCELL( _EQ009);
_EQ009 = !DIR & Q7
# DIR & Q0;
Project Information d:\lu\vhdl-digitallogic\disk\ch6\ch6_4_1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX8000' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,051K
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