ch6_5_2.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch6_5_2 is
	PORT(
		 CP			: IN    STD_LOGIC;		-- CLOCK
		 DIN		: IN    STD_LOGIC;		-- I/P Signal
		 OP			: OUT   STD_LOGIC		-- O/P Signal	
		);
END Ch6_5_2;

--*********************************************
ARCHITECTURE a OF Ch6_5_2 IS
	TYPE 	STATE IS	(S0,S1,S2,S3);		--State Type Declare
	SIGNAL  PresentState 	: STATE; 		-- Present State
	SIGNAL  NextState 		: STATE;		-- Next State
BEGIN
											
	SwitchToNextState : Process (CP)	-- PresentState -> NextState
	BEGIN	
		IF CP'EVENT AND CP = '1' THEN
				PresentState <= NextState;				
		END IF;
	END PROCESS SwitchToNextState;
		

	ChangeStateMode : PROCESS (DIN,PresentState)				
	BEGIN
		CASE PresentState IS
			WHEN S0 =>					--STATE S0
				IF DIN = '0' THEN			--INPUT=0
					NextState <= S0;
					OP <= '0';					--OUTPUT
				ELSE
					NextState <= S1;
					OP <= '1';					--OUTPUT
				END IF;
							
			WHEN S1 =>					--STATE S1
				IF DIN = '1' THEN			--INPUT=1
					NextState <= S1;
					OP <= '1';					--OUTPUT
				ELSE
					NextState <= S2;
					OP <= '0';					--OUTPUT
				END IF;
			
			WHEN S2 =>					--STATE S2
				IF DIN = '1' THEN			--INPUT=1
					NextState <= S2;
					OP <= '0';					--OUTPUT
				ELSE
					NextState <= S3;
					OP <= '1';					--OUTPUT
				END IF;
			
			WHEN S3 =>					--STATE S3
				IF DIN = '1' THEN			--INPUT=1
					NextState <= S0;
					OP <= '1';					--OUTPUT
				ELSE
					NextState <= S1;
					OP <= '0';					--OUTPUT
				END IF;
			
			WHEN OTHERS =>				--Initial State	
				NextState <= S0;
				OP <= '0';					--OUTPUT
	 		END CASE;
		END PROCESS ChangeStateMode; 

END a;