ch6_2_3b.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch6_2_3B is
	PORT(
		 CP, DIR	: IN	STD_LOGIC;
		 Q			: OUT	STD_LOGIC_VECTOR(2 DOWNTO 0) 
		);
END Ch6_2_3B;

--*********************************************
ARCHITECTURE a OF Ch6_2_3B IS
	SIGNAL 		QN		: 	STD_LOGIC_VECTOR(2 DOWNTO 0);   
BEGIN
											
		PROCESS (CP)						-- *** UP/DOWN COUNTER
		BEGIN
				IF CP'event AND CP='1' THEN
					IF DIR = '0' THEN
						QN <= QN + 1;		--COUNTER + 1 
					ELSE						
						QN <= QN - 1;		--COUNTER - 1 
					END IF;
				END IF;
		END PROCESS;			

		Q <= QN ;							-- COUNTER OUTPUT			

END a;