ch2_3_1.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY CH2_3_1 is
	PORT(
			A,B,C 	: IN 	Std_Logic;
			D,E		: OUT	Std_Logic   	
		);
END CH2_3_1;

--*********************************************
ARCHITECTURE a OF CH2_3_1 IS
BEGIN
	D <= A and B;
	E <= not C;
END a;