ch2_1_3.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY CH2_1_3 is
	PORT(
			A : IN 		Std_Logic_Vector(1 DOWNTO 0);   	
			B : IN  	Unsigned(1 DOWNTO 0); 					 		
		 	C : OUT  	Unsigned(7 DOWNTO 0);
			D : OUT     Std_Logic_Vector(1 DOWNTO 0)	
		);
END CH2_1_3;

--*********************************************
ARCHITECTURE a OF CH2_1_3 IS
	SIGNAL E,F,G	: Unsigned(1 DOWNTO 0);
	SIGNAL H 		: Unsigned(7 DOWNTO 0);
BEGIN
	E <= Unsigned (A);					--(1)
	F <= B;								--(2)
		
	H(1 DOWNTO 0) <= E+F; 				--(3)
	H(3 DOWNTO 2) <= E-F; 				--(4)
	H(7 DOWNTO 4) <= E*F; 				--(5) 

	G(0) <= E(0) AND F(0); 				--(6)
	G(1) <= E(1) OR F(1);				--(7)
	
	C <= H;								--(8)
	D <= Std_Logic_Vector (G);			--(9)
	
END a;