ch2_1_2.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY CH2_1_2 is
	PORT(
			A : IN 		STD_LOGIC_VECTOR(3 DOWNTO 0);   	
			B : IN  	STD_LOGIC_VECTOR(3 DOWNTO 0); 					 		
		 	C : OUT  	STD_LOGIC_VECTOR(7 DOWNTO 0)			
		);
END CH2_1_2;

--*********************************************
ARCHITECTURE a OF CH2_1_2 IS
BEGIN
	C(0) <= Not A(0);
	C(2 downto 1) <= A(2 downto 1) and B(2 downto 1);	
	C(3) <= '1' xor A(3) ;
	
	C(7 downto 4) <= "1111" WHEN (A /= B) else
					 "0000";
END a;