ch2_3_2.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY CH2_3_2 is
	PORT(
			X,Y 	: IN 	Std_Logic;
			Z		: OUT	Std_Logic   	
		);
END CH2_3_2;

--*********************************************
ARCHITECTURE a OF CH2_3_2 IS
BEGIN
 
	Z <= '0' When (X='0' and Y='0') Else
		 '1' When (X='0' and Y='1') Else
		 '1' When (X='1' and Y='0') Else
		 '0';		 
		
END a;