ch2_2_1.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY CH2_2_1 is
	PORT(
			A : IN 		Std_Logic;   	
			B : IN  	Std_Logic; 					 		
		 	C : IN  	Std_Logic;
			F : OUT     Std_Logic	
		);
END CH2_2_1;

--*********************************************
ARCHITECTURE a OF CH2_2_1 IS
	SIGNAL D,E		: Std_Logic;
BEGIN
	D <= A and B;					--(1)
	E <= not C;						--(2)
	
	F <= D or E;					--(3)
END a;