ch2_4_1.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY CH2_4_1 is
	PORT(
			A,RST1	: IN 	Std_Logic;
			OP1	: OUT	Std_Logic   	
		);
END CH2_4_1;

--*********************************************
ARCHITECTURE a OF CH2_4_1 IS
	
BEGIN
	Process 
	Begin
		OP1 <= A;

		WAIT UNTIL RST1 ='1';
	End Process;

END a;