ch2_3_3.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY CH2_3_3 is
	PORT(
			S 		: IN 	Std_Logic_Vector(1 Downto 0);
			Z		: OUT	Std_Logic   	
		);
END CH2_3_3;

--*********************************************
ARCHITECTURE a OF CH2_3_3 IS
BEGIN
 
	With S Select 
		Z <= '0' When "00",
			 '1' When "01",
			 '1' When "10",
			 '0' When Others;
END a;