ch2_5_1.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY CH2_5_1 is
	PORT(
			D0,D1		: IN 	Std_Logic;
			S			: IN 	Std_Logic_VECTOR(1 Downto 0);
			OP			: OUT	Std_Logic   	
		);
END CH2_5_1;

--*********************************************
ARCHITECTURE a OF CH2_5_1 IS
	Signal A : Std_Logic;
BEGIN
	Process (S)
	Begin
		Case S Is
			When "00" =>
				A <= D0;
			When "01" =>
				A <= D1;
			When "10"  =>
				A <= Not A;
			When Others =>	
				A <= '0';	
		End Case;
	End Process;

	OP <= A;

END a;