📄 ch2_1_2.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch2\ch2_1_2.rpt
ch2_1_2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 4/ 48( 8%) 0/ 48( 0%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch2\ch2_1_2.rpt
ch2_1_2
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
-- Node name is 'C0~1'
-- Equation name is 'C0~1', location is LC1_A2, type is buried.
-- synthesized logic cell
_LC1_A2 = LCELL( A0);
-- Node name is 'C0'
-- Equation name is 'C0', type is output
C0 = !_LC1_A2;
-- Node name is 'C1'
-- Equation name is 'C1', type is output
C1 = _LC3_A4;
-- Node name is 'C2'
-- Equation name is 'C2', type is output
C2 = _LC5_A3;
-- Node name is 'C3~1'
-- Equation name is 'C3~1', location is LC7_A2, type is buried.
-- synthesized logic cell
_LC7_A2 = LCELL( A3);
-- Node name is 'C3'
-- Equation name is 'C3', type is output
C3 = !_LC7_A2;
-- Node name is 'C4'
-- Equation name is 'C4', type is output
C4 = !_LC5_A1;
-- Node name is 'C5'
-- Equation name is 'C5', type is output
C5 = !_LC3_A1;
-- Node name is 'C6'
-- Equation name is 'C6', type is output
C6 = !_LC1_A1;
-- Node name is 'C7'
-- Equation name is 'C7', type is output
C7 = !_LC7_A1;
-- Node name is ':118'
-- Equation name is '_LC5_A3', type is buried
_LC5_A3 = LCELL( _EQ001);
_EQ001 = A2 & B2;
-- Node name is ':119'
-- Equation name is '_LC3_A4', type is buried
_LC3_A4 = LCELL( _EQ002);
_EQ002 = A1 & B1;
-- Node name is '~154~1'
-- Equation name is '~154~1', location is LC2_A1, type is buried.
-- synthesized logic cell
_LC2_A1 = LCELL( _EQ003);
_EQ003 = !A3 & B3
# A3 & !B3
# A2 & !B2
# !A2 & B2;
-- Node name is '~154~2'
-- Equation name is '~154~2', location is LC3_A1, type is buried.
-- synthesized logic cell
!_LC3_A1 = _LC3_A1~NOT;
_LC3_A1~NOT = LCELL( _EQ004);
_EQ004 = A1 & !B1
# !A1 & B1
# !_LC4_A1
# _LC2_A1;
-- Node name is '~154~3'
-- Equation name is '~154~3', location is LC1_A1, type is buried.
-- synthesized logic cell
!_LC1_A1 = _LC1_A1~NOT;
_LC1_A1~NOT = LCELL( _EQ005);
_EQ005 = A1 & !B1
# !A1 & B1
# !_LC4_A1
# _LC2_A1;
-- Node name is '~154~4'
-- Equation name is '~154~4', location is LC7_A1, type is buried.
-- synthesized logic cell
!_LC7_A1 = _LC7_A1~NOT;
_LC7_A1~NOT = LCELL( _EQ006);
_EQ006 = A1 & !B1
# !A1 & B1
# !_LC4_A1
# _LC2_A1;
-- Node name is ':154'
-- Equation name is '_LC5_A1', type is buried
!_LC5_A1 = _LC5_A1~NOT;
_LC5_A1~NOT = LCELL( _EQ007);
_EQ007 = _LC2_A1
# !_LC4_A1
# A1 & !B1
# !A1 & B1;
-- Node name is ':158'
-- Equation name is '_LC4_A1', type is buried
!_LC4_A1 = _LC4_A1~NOT;
_LC4_A1~NOT = LCELL( _EQ008);
_EQ008 = !A0 & B0
# A0 & !B0;
Project Information d:\lu\vhdl-digitallogic\disk\ch2\ch2_1_2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,090K
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