ch2_2_3.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY CH2_2_3 is
	PORT(
			IP : IN 	Std_Logic;
			CP : IN		Std_Logic;   	
			OP : OUT  	Std_Logic 					 		
		);
END CH2_2_3;

--*********************************************
ARCHITECTURE a OF CH2_2_3 IS
BEGIN
	Process (CP,IP)
		Variable D		: Std_Logic;
	Begin
		IF CP'EVENT AND CP ='1' THEN
			D := IP;
			OP <= D;
		END IF;
	End Process;

END a;